Pawan Kishore Singh

c/o Microelectronics Office, Department of Electrical Engineering

Indian Institute of Technology Bombay, Mumbai - 400076 India

Email: pawan@ee.iitb.ac.in • Ph: +91-9769509595

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Objective

A research and development position in the field of novel semiconductor device technology development and reliability study.

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Education

2006 – Present Ph.D student in Electrical Engineering, IIT Bombay                               CGPA: 9.47/10

Research Focus: Fabrication and Characterization of Metal Nanocrystal Flash Memory

Completion anticipated: August 2009

2001 – 2006 Dual Degree (B.Tech + M.Tech) in Electrical Engineering, IIT Bombay CGPA: 8.20/10

Major: Microelectronics, Dissertation Title: Reliability of Nanocrystal Flash EEPROMs

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Research Experience

• Fabrication and characterization of metal nanocrystal (NC) Flash memory                         (Ph.D. Research)

Prof. Souvik Mahapatra, Prof. Anil Kottantharayil,

• Investigated the formation of metal NC and obtained related size and area coverage statistics
• Development and integration of Aluminum Oxide film suitable for memory application
• Fabrication of single layer and dual layer metal NC Flash memory devices
• Performed electrical characterization and  reliability assessment of metal NC flash devices
• Suggested new structures and materials for improving the NC flash reliability
• Scaling of memory devices for NAND application                                                         (Dual Degree)

Prof. Souvik Mahapatra and Prof. Won Jong Yoo

o Fabricated charge trap flash and metal nanocrystal flash memory devices with gate length L ≥ 60nm

o Evaluated impact of device size scaling on nanocrystal/charge trap flash memory under NAND operation

o Contributed to the development of 3-D NC memory simulator

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Work Experience

Jul 2008 – Present           Teaching Assistant, Indian Institute of Technology Bombay, India

Jun 2007 – Jul 2008        Graduate Intern and Trainee, Applied Materials, Santa Clara, CA, USA

Jan 2005 – Jul 2005        Intern (Exchange Student), National University of Singapore, Singapore

May 2003 – Jul 2003      Summer Intern, Indian Institute of Technology Delhi, India

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Technical Skills

• Characterization Performed characterization of Flash memory devices under NAND and NOR operation, hot carrier, gate oxide reliability and charge pumping measurements.
• Fabrication Proficient in theory and operation of Physical Vapor Deposition (sputtering), Rapid Thermal Processing and Chemical Vapor Deposition tools and techniques.
• Computer Languages Knowledge of C/C++, and MATLAB programming
• Simulations ISE-TCAD and SENTAURUS (process and device)

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Major Publications

1. P K Singh, R Hofmann, G Bisht, K K Singh, N Krishna, S Mahapatra, “Performance and Reliability of Au and Pt Single Layer Metal Nanocrystal Flash Memory under NAND (FN/FN) Operation,” under review IEEE Transactions On Electron Devices (IEEE TED)
2. P K Singh, G Bisht, R Hofmann, K Singh, S Mahapatra, “Dual Layer Pt metal NC Flash for MLC NAND application”, in Intl. Memory Workshop (IMW) 2009 (to be presented).
3. P K Singh, G Bisht, Sivatheja M, Sandhya C, R Hofmann, K Singh, G Mukhopadhyay, N Krishna, S Mahapatra,, “Reliability of SL and DL Pt NC Devices for NAND Flash Applications: A 2-Region Model for Endurance Defect Generation”, in IEEE Intl. Reliability Physics Symposium (IRPS) 2009 (to be presented).
4. P K Singh, G Bisht, K K Singh, R Hofmann, N Krishna and S Mahapatra, “Metal Nanocrystal Memory with Pt Single- and Dual-Layer NC with Low-Leakage Al₂O₃ Blocking Dielectric”, in IEEE Electron Device Letters (IEEE EDL), vol. 29, pp. 1389-1391 Dec. 2008.
5. P K Singh, K K Singh, R Hofmann, K Armstrong, N Krishna and S Mahapatra, “Au Nanocrystal Flash Memory Reliability and Failure Analysis”, in IEEE Intl. Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA) 2008.
6. P K Singh, K Singh, R Hofmann, K Armstrong, S Mahapatra, and N Krishna, “Aluminum Oxide thin films using Sputtering technique as blocking oxide for Flash memory applications”, in MRS spring symposium 2008 (San Francisco).
7. Sandhya C, U Ganguly, K K Singh, P K Singh, C Olsen, S M Seutter, R Hung, G Conti, K Ahmed, N Krishna, J Vasi and S Mahapatra, “Nitride engineering and the effect of interfaces on charge trap flash performance and reliability” in IEEE International Reliability Physics Symposium (IRPS) 2008, pp. 406-411.
8. A Nainani, S Palit,  P K Singh, U Ganguly, N Krishna, J Vasi, and S Mahapatra, “Development of a 3D simulator for metal nanocrystal (NC) flash memories under NAND operation”, IEEE International Electron Devices Meeting (IEDM) 2007, pp. 947-950.
9. P K Singh, A Nainani, “Extensive reliability analysis of Tungsten dot NC devices embedded in HfAlO high-k dielectric under NAND (FN/FN) operation”, in IEEE Intl. Symposium on the Physical and Failure Analysis of Integrated Circuits  (IPFA) 2007, pp. 197-201.
10. Z Gang, S K Samanta, P K Singh, F-J Ma, M-T Yoo, Y Roh, W J Yoo, “Partial crystallization of HfO₂ for two-bit/four-level SONOS-type flash memory”, in IEEE Transactions on Electron Devices (IEEE TED), vol. 54, pp. 3177 – 3185, Dec. 2007.
11. A Nainani, A Roy, P K Singh, G Mukhopadhyay, J Vasi, “Electrostatics and its effect on spatial distribution of tunnel current in metal Nanocrystal flash memories”, in IEEE Intl. Conference on Memory Technology and Design (ICMTD) 2007, pp. 251-254.
12. S K Samanta, P K Singh, W J Yoo, G Samudra, Y-C Yeo, L K Bera, and N Balasubramanian, "Enhancement of Memory Window in Short Channel Non-Volatile Memory Devices Using Double Layer Tungsten Nanocrystals", in IEEE International Electron Devices Meeting (IEDM) 2005,  pp. 170-173
13. Y Q Wang, P K Singh, W J Yoo, Y-C Yeo, G Samudra, A Chin, W S Hwang, J H Chen, S J Wang, D L  Kwong, "Long retention and low voltage operation using IrO₂/HfAlO/HfSiO/HfAlO gate stack for memory application", in IEEE International Electron Devices Meeting (IEDM) 2005, pp. 162-165.

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Talks

§ Applied Materials Inc., Santa Clara 2008

§ Nanyang Technological Univ., Singapore 2008

§ FCR College of Engineering, Mumbai 2008

§ Intel, Santa Clara 2008

§ Purdue University, West Lafayette, 2007

§ National Univ. of Singapore, 2005

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Honours and Awards

§ Awarded Applied Materials Fellowship for Ph.D. in IIT Bombay

§ Awarded Applied Material Certificate of Excellence for work on metal nanocrystal memory

§ Authored/co-authored 17 refereed journal and conference papers

§ Selected for National Univ. of Singapore - IIT Bombay student exchange from many applicants

§ All India Rank 325 (top 0.3%) for admission to the reputed Indian Institutes of Technology

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Positions of Responsibility

§ Mentoring two PhD, and four Masters students towards the completion of their respective projects

§ Reviewer for the IEEE Transactions on Electron Devices

§ Led the device characterization laboratory in IIT Bombay (2006 – 2007)

§ Hostel student councilor (Cultural) (2003 – 2004)

§ Coordinator competitions (2002), and accounts (2003) in Mood Indigo, student festival of IIT Bombay

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References

            Available on request