Maryam Shojaei Baghini

• Technology-aware design (device circuit co-design); integrated circuits and system design with emerging devices
• Analog/Mixed-signal VLSI design and test
  (SoC, LV, LP, LE, Biomedical/Biosensors, Bio-inspired circuits and systems, I/O, highly-precise circuits & systems, instrumentation, energy harvesting and many more applications)
• Specific technologies and performance-optimized analog/mixed-signal/RF circuits & systems for healthcare applications
• Integrated power management for SOC applications
• High-speed data transmission and interconnects
• Circuit and system modeling/optimization
• Circuit and system design with organic thin film components
• RF/Microwave integrated circuit design
• Analog aspects of digital circuits
• Sensor-Circuit Integration
• Analog/Mixed-signal/RF EDA (CAD tools, theory and implementation)
• VLSI design and embedded systems

1. EE719/410, Mixed-Signal VLSI Design (Live EDUSAT course, record, broadcast and webcast by CDEEP IIT-B)
2. EE618, Analog VLSI Design (record and webcast by CDEEP IIT-B)
3. EE705, VLSI Design Lab (record and webcast by CDEEP IIT-B)
4. EE232, Analog Electronics (Live EDUSAT course, record and broadcast by CDEEP IIT-B)
5. EE707, MEDT (record and webcast by CDEEP IIT-B)
6. EE318, Electronic Design Lab
7. Associate instructor for EE236, EDL Lab
   

Link to syllabus of all courses: http://www.ee.iitb.ac.in/curriculum.html

• Post Doc. Research (Dept. of Electrical Engineering, IIT-Bombay)
• Ph.D. and M.S., both in Electrical Engineering (Major: Electronics), Sharif Univ. of Technology
• B. S., Electrical Engineering (Major: Electronics), S. B. Univ. of Kerman

• Associate Professor in E.E. Department of IIT-B (at present)
• Assistant Professor in E.E. Department of IIT-B
• Member of team of designers for commercial chips in industry (all of the designs have been fabricated and tested successfully).
• Academic Experience in IIT-B and other Institutes and Universities

1. Dr. A. B. Sachid (Graduated in 2010, Guides: V. Rampgopal Rao and M. Shojaei Baghini)
   Joined Post-Doctoral Research Program at Univ. of California, Berkeley.
2. Dr. Mayank Shrivastava (Graduated in 2010, Guides: V. Rampgopal Rao and M. Shojaei Baghini)
   Joined Intel, Germany/USA.
3. Dr. Rajesh Thakker (QIP, Graduated in 2009, Guides: Mahesh B. Patil and M. Shojaei Baghini)
   Rejoined as Associate Professor, EC Department, V.G.E.C., Chandkheda, Ahmedabad.

1. M. Bakshi (Guides: V. R. Sule, M. Shojaei baghini)
2. S. Boyapati (Guides: M. Shojaei Baghini and Jean-Michel Redoute (Monash University, Australia)) (under IITB-Monash Research Academy)
3. M. V. Dave (Guides: Dinesh K. Sharma and M. Shojaei Baghini)
4. A. Gupta (Guides: M. Shojaei Baghini and V. Rampgopal Rao)
5. V. G. Hande
6. T. K. Harishbhai (Guides: V. Rampgopal Rao and M. Shojaei Baghini)
7. R. R. Navan (Guides: V. Rampgopal Rao and M. Shojaei Baghini)
8. P. S. Swain (Guides: M. Shojaei Baghini and V. Rampgopal Rao)

• Supervision/Co-Supervision of 29 completed MTech/DD projects (from 2006)
• Graduated students: (as per alphabetical order) currently in AMCC-India, Broadcom-India, Cadence-India, Cosmic Circuits, IBM-India, Intel-India, Philips-India, Rambus-India, Samsung-India, Techtronics, TI-India and TS-India / or pursuing for higher education.

• 2 research projects with industry and 1 interuniversity research project were completed in 2010.

• Research under support from IRCC_IIT-Bombay (1 project)
• DIT funded research
  (2 projects, Joint research with V. Ramgopal Rao and Dinesh K. Sharma)
• DST funded research
  (1 project, Joint research with Girish Kumar)
• MNRE funded Research under NCPRE
  (1 project, Joint research with Swaroop Ganguly)
• Industry funded research under IITB-industry collaborations
  (2 individual projects and 1 joint project with V. Ramgopal Rao)
• Contribution in research with other institutes under INUP (1 project)
• Collaboration with other universities (1 project)

1. Test chip SC_IITB_2: Ultra low-noise ultra low-power INA and buffer, rail-to-rail active filter stage and RLD modules for biomedical and sensor applications (Sanjay Joshi, Viral Thaker, Mugdha Nazre, M. Shojaei Baghini (with special thanks to Marshnil V. Dave))
2. Test chip CMS2: Uni/Bi-directional low-power, PVT-compensated high-speed CM signaling (Marshnil V. Dave, M. Shojaei Baghini, Dinesh K. Sharma)
3. Test chip: High-speed comparator and offset compensation circuit (Santosh K. Gowdhaman, M. Shojaei Baghini (with special thanks to Marshnil V. Dave))
4. Test chip CMS1: Unidirectional low-power high-speed CM signaling (Marshnil V. Dave, M. Shojaei Baghini, Dinesh K. Sharma)
5. Test chip SC_IITB_1: (M. Shojaei Baghini, Rakesh K. Lal, Dinesh K. Sharma) (INA module in SC_IITB_1 had minimum PD compared to already-reported IAs). Test chip SC_IITB_1 was fabricated, tested and used as a complete signal conditioning chip for simultaneous three-lead ECG recording as a part of SiLoc project (Internal link to SiLoc project and team members: http://sharada.ee.iitb.ac.in/~siloc/).

1. Project guide and co-recipient of the first place award all over India in Cadence Design Contest-India (2011).
2. Project guide for one of the finalist projects in international chip design competition in ISIC, Singapore (2011).
3. Project guide and co-recipient of the first place award in Anveshan Design Contest held by Analog Devices-India all over India (Healthcare category), 2010-2011
4. Co-recipient of the best paper award, IEEE ISVLSI Symposium, India (2011).
5. Project guide and co-recipient of the runner up award all over India in Cadence Design Contest-India (2010).
6. Co-recipient of IIT-Bombay industry impact award (2008).
7. Co-recipient of the best research award in the circuit design category, Intel Corporation AAF, Taiwan (2008).
8. Guide for the winner project of the first Cadence Student Design Contest among SAARC countries (2006).
9. Co-recipient of the third award on Research and Development in 15th international festival of Kharazmi (2002).

Anvesha Amaravati
* First place in Student Project Contest in International Conference on VLSI Design 2012, India.
* First place in Cadence Design Contest all over India (Master category), 2011.
Anvesha Amaravati and Deepesh Kamani
* First place in Anveshan Design Contest and Fellowship Program held by Analog Devices all over India (healthcare category), 2010-2011.

Priyanka Kabara and Sanket Thakur
* One of finalist teams in Student Project Contest in International Conference on VLSI Design 2012, India.

Vineeth Anavangot
* Winner of the second prize in Nebula’11 by Cosmic Circuits all over India.

Ani Xavier
* One of finalists in Nebula’11 by Cosmic Circuits all over India.

Sanjay Joshi and Viral P. Thaker (Graduated in 2011)
* One of finalist teams in international chip design competition in ISIC-2011, Singapore.
* Runner up place all over India in Cadence-India design contest, 2010, (Master project category all over India).

Dr. Aangada B. Sachid (Graduated in 2010, Guides: V. Rampgopal Rao and M. Shojaei Baghini)
* Best Ph.D. thesis award, E.E. Department, IIT-Bombay, 2011.
* The best TA award in EE Dept., IIT-Bombay in 2008.
* Co-recipient of the best research award in the circuit design category, Intel Corporation AAF, Taiwan (2008).

Naveen K. Kancharapu (Graduated in 2011, Guides: M. Shojaei Baghini and Dinesh K. Sharma)
Best Paper Award in IEEE ISVLSI Symposium, 2011, India
Naveen K. Kancharapu, Marshnil V. Dave, Veerraju Masimukkula, M. Shojaei Baghini, Dinesh K. Sharma

Dr. Mayank Shrivastava (Graduated in 2010, Guides: V. Rampgopal Rao and M. Shojaei Baghini)
* Ph.D. Excellence Thesis Work, E. E. Department, IIT-Bombay, 2010.
* Dr. Mayank Srivastava has been awarded as one of the finalists of the first India TR35 list, 2010.
* He’s also listed in “2000 Outstanding Intellectuals of the 21st Century-2010“-
Biography publication by International Biographical Center (IBC), Cambridge, England.
* Co-recipient of the best research award in the circuit design category, Intel Corporation AAF, Taiwan (2008).

Santosh K. Gowdhaman (Graduated in 2010)
* Winner of the third prize in Nebula’09 by Cosmic Circuits all over India.

Dr. Rajesh Thakker (Graduated in 2009, Guides: M. B. Patil and M. Shojaei Baghini))
* Co-recipient of the best research award in the circuit design category, Intel Corporation AAF, Taiwan (2008).

1. One of members/developers of on-going NPTEL project team in IIT-Bombay
2. One of members/developers of on-going Virtual Lab project team in IIT-Bombay
3. One of members of NCPRE project supported by MNRE http://www.ncpre.iitb.ac.in/
4. Invited TPC member, Emerging Applications and Technologies sub-committee, IEEE A-SSCC
   (Sister conference of IEEE ISSCC)http://www.a-sscc.org/
5. Invited TPC member, Low-Power Design/Circuits and Technology Track, IEEE Int. Conf. on VLSI Design
   (Sister conference of IEEE DAC)http://www.vlsiconference.com/
6. Invited TPC member, Circuit and System Design, IEDEC and ISQED Conference) http://www.isqed.org/ , http://www.iedec.org/
7. Invited TPC member, ASQED Conference http://www.asqed.com/
8. Invited TPC member, Nanoelectronics Track, IEEE ICM Conference http://www.ieee-icm.com/
9. Invited member of Synopsys Curricula Advisory Board
10. Invited track chair (Analog and Mixed-Signal System Design) and TPC member, ISED http://ised.seedsnet.org/
11. Invited lectures and talks
12. Reviewer: Journals and conferences (IEEE and other technical societies/publishers)
13. Book Reviewer
14. Senior Member of IEEE

• Monograph Title: Applications of Evolutionary Algorithms in VLSI
  by R. Thakker, M. B. Patil and M. Shojaei Baghini
  In press by LAMBERT Academic Publishing, ISBN 978-3-8454-0434-9, 2010

• Invited Chapter Title: Hardware Development of Wearable ECG Devices
  by M. Shojaei Baghini, D. K. Sharma, R. K. Lal
  Monograph Title: Ambulation Analysis in Wearable ECG by S. Chaudhuri, T. Pawar, S. P. Duttagupta
  Publisher: Springer, ISBN: 978-1-4419-0723-3, August 2009

• Inventor/co-inventor of 13 filed patent applications.

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1. “A Variation Tolerant Current-Mode Signaling Scheme for On-chip Interconnects”, M. Dave, M. Jain, M. Shojaei Baghini, D. K. Sharma, Accepted for publication in IEEE Transactions on VLSI Systems, 2012.
   
   
2. “A Process and Temperature Compensated Current Reference Circuit in CMOS Process”, M. Dave, M. Shojaei Baghini, D. K. Sharma, Accepted for publication in Elsevier Microelectronics Journal, 2011.
   
   
3. “Current Actuation Method for ΔR Measurement in Piezo-Resistive Sensors with a 0.3 ppm Resolution”, N. A. Gilda, S. Nag, S. Patil, M.Shojaei Baghini, D. K. Sharma, V. Ramgopal Rao, Accepted for publication in IEEE Transactions on Instrumentation & Measurement, 2011.
   
   
4. “Mobility Enhancement of Solution-Processed Poly (3-hexylthiophene) Based Organic Transistor using Zinc Oxide Nanostructures”, R. R. Navan, B. Panigrahy, M. Shojaei Baghini, D. Bahadur and V. Ramgopal Rao, Accepted for publication in Elsevier Journal of Composites B: Engineering, 2011.
   
   
5. “Towards System on Chip (SoC) Development Using FinFET Technology: Challenges, Solutions, Process Co-Development & Optimization Guidelines”, M. Shrivastava, R. Mehta, S. Gupta, N. Agrawal, M. Shojaei Baghini, D. K. Sharma, T. Schulz, K. Arnim, W. Molzer, H. Gossner, V. Ramgopal Rao, IEEE Transactions on Electron Devices, June 2011 (This paper is recognized as feature article in Synopsys newsletter, May 2011).
   
   
6. “A Novel Architecture for Improving Slew Rate in FinFET-based Op-Amps and OTAs”, R. A. Thakker, M. Srivastava, K. H. Tailor, M. Shojaei Baghini, D. K. Sharma, V. Ramgopal Rao, M. B. Patil Elsevier Microelectronics Journal, May 2011.
   
   
7. “A Solution Towards the OFF State Degradation in Drain extended MOS Device”, M. Shrivastava, R. Jain, M. Shojaei Baghini, H. Gossner and V. Ramgopal Rao, IEEE Transactions on Electron Devices, December 2010.
   
   
8. “Complementary Organic Circuits using Evaporated F16CuPc and Inkjet Printing of PQT”, H.S. Tan, B.C. Wang, S. Kamath, J. Chua, M. Shojaei Baghini, V. R. Rao, N. Mathews, S.G. Mhaisalkar, IEEE Electron Device Letters, November 2010.
   
   
9. “Part I: On the Behavior of STI Type DeNMOS Device under ESD Conditions”, M. Shrivastava , H. Gossner, M. Shojaei Baghini, V. Ramgopal Rao, IEEE Transactions on Electron Devices, September 2010.
   
   
10. “Part II: On the 3D filamentation and failure modeling of STI Type DEMOS device under various ESD conditions”, M. Shrivastava , H. Gossner, M. Shojaei Baghini, V. Ramgopal Rao, IEEE Transactions on Electron Devices, September 2010.
    
    
11. “Comments on “Improved Accuracy Pseudo-Exponential Function Generator with Applications in Analog Signal Processing”“, N. V. Karanjkar, R. R. Sahoo and M. Shojaei Baghini, IEEE Transactions on VLSI, September 2010.
    
    
12. “Comments on “An Analog 2-D DCT Processor””, S. P. Noolu, M. Shojaei Baghini, IEEE Transactions on Circuits and Systems in Video Technology, August 2010.
    
    
13. “A Novel Bottom Spacer FinFET Structure For Improved Short Channel, Power-Delay & Thermal Performance”, M. Shrivastava, M. Shojaei Baghini, D. K. Sharma, V. Ramgopal Rao, IEEE Transactions on Electron Devices, June 2010.
    
    
14. “A Table-Based Approach to Study the Impact of Process Variations on FinFET Circuit Performance”, R. A. Thakker, C. Sathe, M. Shojaei Baghini, M. B. Patil, IEEE Transactions on Computer-aided Design of Integrated Circuits and Systems, April 2010.
    
    
15. “Part I: Mixed Signal Performance of Various High Voltage Drain Extended MOS Devices”, M. Shrivastava, M. Shojaei Baghini, H.Gossner, V. Ramgopal Rao, IEEE Transactions on Electron Devices, Feb. 2010.
    
    
16. “Part II: A Novel Scheme to Optimize the Mixed Signal Performance and Hot Carrier Reliability of Drain Extended MOS Devices”, M. Shrivastava, M. Shojaei Baghini, H.Gossner, V. Ramgopal Rao, IEEE Transactions on Electron Devices, Feb. 2010.
    
    
17. “A Novel Table–Based Approach for Design of FinFET Circuits”, R. A. Thakker, C. Sathe, A. B. Sachid, M. Shojaei Baghini, V. R. Rao, M. B. Patil, IEEE Transactions on Computer-aided Design of Integrated Circuits and Systems, July 2009.
    
    
18. “Automatic Design of Low-Power Low-Voltage Analog Circuits using PSO with Re-initialization”, R. A. Thakker, M. Shojaei Baghini, M. B. Patil, Journal of Low-Power Electronics, Oct. 2009 - Special Issue on International Conference on VLSI Design 2009.
    
    
19. “An Ultra Low-Power Current-Mode Integrated CMOS Instrumentation Amplifier for Personal ECG Recorders”, M. Shojaei Baghini, S. Nag, R. K. Lal, D. K. Sharma, World Scientific Journal of Circuits, Systems, and Computers, Dec. 2008.
    
    
20. “A Novel and Robust Approach for Common Mode feedback using IDDG FinFET”, M. Srivastava, M. Shojaei Baghini, A. B. Sachid, D. K. Sharma, V. R. Rao, IEEE Transactions on Electron Devices, Nov. 2008.
    
    
21. ”Evaluation of the impact of layout on device and analog circuit performance with lateral asymmetric channel MOSFETs”, D. V. Kumar, K. Narasimhulu, P. S. Reddy, M. Shojaei Baghini, D. K. Sharma, M. B. Patil, V. R. Rao, IEEE Transactions on Electron Devices, July 2005.
    
    
22. “A mixed algorithmic and knowledge-based approach for automatic design of analog circuits based on a behavioral model”, M. Shojaei Baghini, M. Sharif-Bakhtiar, Scientia Iranica (International Journal of Science and Technology), Jan. 1999.

TECHNOLOGY-AWARE DESIGN (DEVICE-CIRCUIT CO-DESIGN)

1. A. B. Sachid, P. Paliwal, S. Joshi, M. Shojaei Baghini, D. K. Sharma, V. Ramgopal Rao, “Circuit Optimization at 22nm Technology Node”, Proc. of IEEE Int. Conf. on VLSI Design 2012 (Sister Conf. of IEEE DAC), India.
   
   
2. N. A Gilda, S. Surya, S. Joshi, V. Thaker, M. Shojaei Baghini, D. K.Sharma, V.Ramgopal Rao, “A Low-Cost, Ultra Sensitive Hand-Held System for Explosive Detection using Piezo-Resistive Micro-Cantilevers”, Proc. of ISOCC 2011, South Korea (Invited Paper) .
   
   
3. M. Shojaei Baghini, “Moving Towards 22 nm Node - I/O and ESD Performance”, Tutorial, IEEE International Conf. on VLSI Design 2011 (Sister Conf. of IEEE DAC), India. (Acknowledgment: Mayank Shrivastava, H. Gossner, S. Bychikhin, V. Ramgopal Rao, D. K. Sharma).
   
   
4. Y. D. Rawal, M. Shojaei Baghini, S. Ganguly, “Fabrication & Characterization of MIM Tunnel Diodes”, BangaloreNano 2010, India.
   
   
5. M. Shrivastava, H. Gossner, M. Shojaei Baghini, V. Ramgopal Rao, “3D TCAD Based Approach for the Evaluation of Nanoscale Devices During ESD Failure”, Proc. of ISOCC 2010, South Korea (Invited Paper) .
   
   
6. A. B. Sachid, M. Shojaei Baghini, D. K. Sharma, V. Ramgopal Rao, “Alternate Scaling Strategies for Multi-Gate FETs for High-Performance and Low-Power Applications”, Proc. of ISOCC 2010, South Korea (Invited Paper) .
   
   
7. M. Shrivastava, H. Gossner, M. Shojaei Baghini, V. Ramgopal Rao, “On the Transient Behavior of Various Drain Extended MOS Devices under the ESD stress condition”, Proc. of ISOCC 2010, South Korea (Invited Paper) .
   
   
8. S. Prajapati, R.A.Thakker, M. Shojaei Baghini, M.B.Patil, “Performance Evaluation of FinFET and Planar MOSFET Devices at Circuit Level for 45nm Technology”, Proc. of IEEE/VSI VDAT Symposium 2010, India.
   
   
9. M. Shrivastava, J. Schneider, M. Shojaei Baghini, H. Gossner, V. Ramgopal Rao, “On the failure mechanism and current instabilities in RESURF type DeNMOS device under ESD conditions”, Proc. of IEEE IRPS 2010, USA.
   
   
10. M. Shrivastava, S. Bychikhin, D. Pogany, J. Schneider, M. Shojaei Baghini, H. Gossner, E. Gornik, V. Ramgopal Rao, “On the differences between 3D filamentation and failure of n & p type drain extended MOS devices under ESD condition”, Proc. of IEEE IRPS 2010, USA.
    
    
11. A. B. Sachid, R. A. Thakker, C. Sathe, M. Shojaei Baghini, D. K. Sharma, V. R. Rao, M. B. Patil, “Auto-BET-AMS: An Automated Device and Circuit Optimization Platform to Benchmark Emerging Technologies for Performance and Variability using an Analog and Mixed-Signal Design Framework”, Proc. of IEEE ISQED 2010, USA.
    
    
12. M. Shrivastava, B. Verma, M. Shojaei Baghini, C. Russ, D. K. Sharma, H. Gossner, V. R. Rao, “Benchmarking The Device Performance at Sub 22 nm Node Technologies Using an SoC Framework”, Proc. of IEEE IEDM 2009, USA.
    
    
13. M. Shrivastava, S. Bychikhin, D. Pogany, J. Schneider, M. Shojaei Baghini, H. Gossner, E. Gornik, V. R. Rao, “Filament Study of STI Type Drain Extended NMOS Device Using Transient Interferometric Mapping”, Proc. of IEEE IEDM 2009, USA.
    
    
14. M. Shrivastava, J. Schneider, R. Jain, M. Shojaei Baghini, H. Gossner, V. R. Rao, “IGBT plugged in SCR device for ESD protection in advanced CMOS technology”, Proc. of EOS/ESD Symposium 2009, USA.
    
    
15. M. Shrivastava, J. Schneider, M. Shojaei Baghini, H. Gossner, V. R. Rao, Highly resistive body STI-n-DeMOS: An optimized DeMOS device to achieve moving current filaments for robust ESD protection”, Proc. of IEEE IRPS 2009, Canada.
    
    
16. M. Shrivastava, J. Schneider, M. Shojaei Baghini, H. Gossner, V. R. Rao, “A New Physical Insight and 3D Device Modeling of STI Type DeNMOS Device Failure under ESD Conditions”, Proc. of IEEE IRPS 2009, Canada.
    
    
17. R. R. Navan, H. N. Raval, M. A. Khaderbad, M. Shojaei Baghini and V. Ramgopal Rao, “Low Voltage Patterned Gate Pentacene Organic Circuits with Hafnium oxide High-K Gate Dielectric”, OSC 2009, UK.
    
    
18. R. R. Navan, K. Prashanthi, A. Rajoriya, M. Shojaei Baghini, V. R. Palkar, V. R. Rao, “A Novel High-K (K > 40) Gate Dielectric for Pentacene Organic Thin Film Transistors”, Proc. of ICCE-17 2009, USA.
    
    
19. A. B. Sachid, G. S. Kulkarni, M. Shojaei Baghini, D. K. Sharma, V. R. Rao, “Highly Robust Nanoscale Planar Double-Gate MOSFET Device and SRAM Cell Immune to Gate-Misalignment and Process Variations”, Proc. of IEEE IEDST 2009, India.
    
    
20. R. R. Navan, R. A. Thakker, S. P. Tiwari, M. Shojaei Baghini, M. B. Patil, S. G. Mhaisalkar, V. R. Rao,
    “DC & Transient Circuit Simulation Methodologies for Organic Electronics”, Proc. of IEEE IEDST 2009, India.
    
    
21. A. B. Sachid, R. Francis, M.Shojaei Baghini, D.K. Sharma, Karl-Heinz Bach, R. Mahnkopf, V. R. Rao, “Sub-20 nm gate length FinFET design: Can high-κ spacers make a difference?”, Proc. of IEEE IEDM 2008, USA.
    
    
22. A. B. Sachid, M. Shrivastava, R. A. Thakker, M. Shojaei Baghini, D. K. Sharma, M.B.Patil, V. R. Rao, “Technology-Aware Design (TAD) for Sub-45nm CMOS Technologies”, Intel Corporation AAF 2008, Taiwan (received the best research paper award in circuit design category) .
    
    
23. M. Shojaei Baghini, M. P. Desai, “Impact of technology scaling on metastability performance of of CMOS synchronizing latches”, Proc. of IEEE International Conf. on VLSI Design 2002 (Sister Conf. of IEEE DAC), India.
    
    
24. N. K. Jha, M. Shojaei Baghini, V. R. Rao, “Performance and reliability of single pocket deep submicron MOSFETs for analog applications”, Proc. of ISPFAIC 2002, Singapore.
    
    

ANALOG/MIXED-SIGNAL/RF VLSI IC DESIGN

1. M. Dave, M. Shojaei baghini, D. K. Sharma, “A Novel Robust Signaling Scheme for High-Speed Low-Power Communication over Long Wires”, Accepted in IEEE ISQED , 2012, USA.
   
   
2. M. Dave, M. Shojaei baghini, D. K. Sharma, “High-Speed Low-Power Robust Signaling for On-chip Long Wires”, Accepted in IEEE ISSCC Student Research Preview, 2012, USA.
   
   
3. M. Arrawatia, V. Diddi, H. Kochar, M. Shojaei Baghini, Girish Kumar, “An Integrated CMOS RF Energy Harvester with Differential Microstrip Antenna and On-Chip Charger”, Proc. of IEEE Int. Conf. on VLSI Design 2012 (Sister Conf. of DAC), India.
   
   
4. P. Kabara, S. Thakur, G. Saileshwar, M. Shojaei Baghini, D. K. Sharma, “CMOS Low-Noise Signal Conditioning with a Novel Differential “Resistance to Frequency” Converter for Resistive Sensor Applications”, Proc. of IEEE ISOCC 2011, South Korea.
   
   
5. S. Joshi, V. Thaker, M. Shojaei Baghini, “Versatile Ultra Low Noise, Low Power Analog Signal Conditioning Chip With Integrated Drivers”, Proc. of IEEE ISIC (one of finalist teams in international chip design competition in ISIC), 2011, Singapore.
   
   
6. V. Hande, M. Shojaei baghini, P. R. Apte, “Design and Optimization of High Precision CMOS Voltage Reference Using Taguchi Orthogonal Array Technique”, Proc. of IEEE ISIC, 2011, Singapore.
   
   
7. H. Joshi, M. Shojaei Baghini, “Versatile Battery Chargers for New Age Batteries”, Proc. of IEEE ISED 2011, India.
   
   
8. N. A. Gilda, S. Patil, Seena V, S. Joshi, V. Thaker, S. Thakur, Anvesha A, M. Shojaei Baghini, D. K. Sharma, V. Ramgopal Rao, “Piezoresistive 6-MNA Coated Microcantilevers with Signal Conditioning Circuits for Electronic Nose”, Proc. of IEEE A-SSCC (Sister conference of IEEE ISSCC), 2011, South Korea.
   
   
9. A. Vishnani, M. V. Dave, M. Shojaei Baghini and D. K. Sharma, “A Fully On-Chip Throughput Measurement System for Multi-Gigabits/s On-Chip Interconnects”, Proc. of IEEE ASQED 2011, Malaysia.
   
   
10. A. Vishnani, M. V. Dave, M. Shojaei Baghini and D. K. Sharma, “On-Chip Test Circuits for Throughput Measurement of high-speed Interconnects”, Proc. of VDAT 2011, India.
    
    
11. N. K. Kancharapu, M. V. Dave, M. Shojaei Baghini and D. K. Sharma, “A Low-Power Low-Skew Current-Mode Clock Distribution Network in 90nm CMOS Technology”, Proc. of IEEE ISVLSI (received the best paper award) 2011, India.
    
    
12. S. Sant, S. Waikar, M. V. Dave, M. Shojaei Baghini and D. K. Sharma, “A 16-Gb/s 9mW Transmitter With FFE in 90nm CMOS Technology for Off-Chip Communication”, Proc. of IEEE ISVLSI 2011, India.
    
    
13. M. Arrawatia, M. Shojaei Baghini, Girish Kumar, “RF Energy Harvesting System From Cell Towers in 900MHz Band”, NCC 2011, India.
    
    
14. M. Arrawatia, M. Shojaei Baghini, Girish Kumar, “RF Energy Harvesting System at 2.67GHz and 5.8GHz”, Proc. of APMC 2010, Japan.
    
    
15. M. V. Dave, M. Jain, R. Satkuri, M. Shojaei Baghini, D. K. Sharma, “Energy Efficient Current-Mode Signaling Scheme”, Proc. of IEEE A-SSCC (Sister conference of IEEE ISSCC), 2010, China.
    
    
16. S. K. Gowdhaman, M. Shojaei Baghini, “6-Bit Low-Power Subranging-ADC with Increased Throughput”, Proc. of IEEE MWSCAS 2010, USA.
    
    
17. M. V. Dave, R. Satkuri, M. Jain, M. Shojaei Baghini, D. K. Sharma, “Low-Power Current-Mode Transceiver for On-chip Bidirectional Buses”, Proc. of ACM/IEEE ISLPED 2010, USA.
    
    
18. S. P. Noolu, M. Shojaei Baghini, V. Rajbabu, “Efficient Analog Architectures for DCT Processing”, Proc. of NASA/ESA AHS 2010, USA.
    
    
19. V. G. Hande, M. Shojaei Baghini, “An Ultra Low-Energy DAC for Successive Approximation ADCs”, Proc. of IEEE ISCAS 2010, France.
    
    
20. M. V. Dave, M. Shojaei Baghini, D. K. Sharma, “A Process Variation Tolerant, High-Speed and Low-Power Current Mode Signaling Scheme for On-chip Interconnects”, Proc. of ACM/IEEE GLSVSLI, 2009, USA.
    
    
21. S. R. Krishna, M. Shojaei Baghini, J. Mukherjee, “Current-Mode CMOS Pipelined ADC”, Proc. of IEEE Eurocon 2009, Russia.
    
    
22. K. Bhattacharyya, J. Mukherjee, M. Shojaei Baghini, “27.1GHz CMOS Distributed Voltage Controlled Oscillators With Body Bias for Frequency Tuning of 1.28GHz”, IEEE MWSCAS 2009, Mexico.
    
    
23. J. Mukherjee, M. Shojaei Baghini, M. Johnson, “Phase Noise Reduction in Quadrature LC Oscillators Using Inverter-Based Tail Noise Shaping”, Proc. of IEEE NEWCAS and TAISA, 2009, France.
    
    
24. K. Bhattacharyya, J. Mukherjee, M. Shojaei Baghini, “Effects of Substrate Bias on Noise of 0.18µm CMOS Devices at Microwave Frequency”, IWPSD 2009, India.
    
    
25. K. Bhattacharyya, J. Mukherjee, M. Shojaei Baghini, “20GHz CMOS Distributed Voltage Controlled Oscillators With Frequency Tuning By MOS Varactors”, Proc. of IEEE IEDST 2009, India.
    
    
26. M. V. Dave, M. Shojaei Baghini, D. K. Sharma, “Low-power current-mode receiver with inductive input impedance”, Proc. of ACM/IEEE ISLPED 2008, India.
    
    
27. R. Satkuri, M. V. Dave, M. Shojaei Baghini, D. K. Sharma, “On-chip Test Circuits for Fast Interconnects”, Proc. of IEEE VDAT 2008, India.
    
    
28. J. Mukherjee, Young-Gi Kim, I. Suh, P. Roblin, Wan-Rone Liou, Yao-Chian Lin, M. Shojaei Baghini “Microstrip Equivalent Parasitic Modeling of RFIC Interconnects”, Proc. of IEEE MWSCAS 2007, Canada.
    
    
29. R. D. Kanphade, M. Shojaei Baghini, D. G. Wakade, M. Chhangani, M. Patil, S. M. Ranjan, J. R. Verma, N. K. Ingole, P. Gawande, “Design of low power FPAA in 0.35u CMOS Process”, Accepted in IASTED ICCSS 2006, USA.
    
    
30. M. Shojaei Baghini, R. K. Lal, D. K. Sharma, “A Low-Power and Compact Analog CMOS Processing Chip for Portable ECG Recorders”, Proc. of IEEE A-SSCC 2005 (Sister Conf. of IEEE ISSCC), Taiwan.
    
    
31. M. Shojaei Baghini, R. K. Lal, D. K. Sharma, “An ultra low-power instrumentation amplifier for biomedical applications”, Proc. of IEEE BioCAS 2004, Singapore.
    
    
32. V. M. Tousi, F. Sahandi, M. Atarodi, M. Shojaei Baghini, “A 3.3V / 1W class D audio power amplifier with 103 dB DR and 90% efficiency”, Proc. of MIEL 2002, Yugoslavia.

EDA/MODELING

1. R. Modak, M. Shojaei Baghini, “A Generic Analytical Model of Switching Characteristics for Efficiency-Oriented Design and Optimization of CMOS Integrated Buck Converters”, Proc. of IEEE ICIT 2009, Australia.
   
   
2. R. A. Thakker, C. Sathe, A. B. Sachid, M. Shojaei Baghini, V. R. Rao, M. B. Patil, “Automated Design and Optimization of Circuits in Emerging Technologies”, Proc. of IEEE ASP-DAC(Sister Conf. of IEEE DAC), 2009, Japan.
   
   
3. R. A. Thakker, M. Shojaei Baghini, M. B. Patil, “Low-Power Low-Voltage Analog Circuit Design using HPSO”, Proc. of IEEE Int. Conf. on VLSI Design 2009 (Sister Conf. of DAC), India.
   
   
4. R. D. Kanphade, M. Shojaei Baghini, D. G. Wakade, M. Chhangani, M. V. Patil, S. M. Ranjan, J. R. Verma, N. K. Ingole, P. Gawande, “Design of FPAA using custom IC and optimization-based design flow”, Proc. of CDNLive 2006, USA.
   
   
5. P. Gawande, M. Chhangani, J. Verma, M. Patil, N. Ingole, M. Shojaei Baghini, R. D. Kanphade, “Design and implementation of low-cost power-optimized OTA-based FPAA in 0.35um MM CMOS process” CDNLive 2006, India, (winner of the First Cadence Design Systems, Inc. Design Contest held among SAARC countries, 2006).
   
   
6. M. Shojaei Baghini, M. Sharif-Bakhtiar, “A method for automatic design of analog circuits based on a behavioral model”, Proc. of IEEE ISCAS 1998, USA.
   
   
7. M. Shojaei Baghini, M. Sharif-Bakhtiar, “Automatic design of analog circuits based on a behavioral model”, Proc. of IEEE CCECE 1998, Canada.
   
   

Department of Electrical Engineering
IIT-Bombay, Powai
Mumbai 400 076, India
Email : mshojaei[AT]ee.iitb.ac.in
Phone (Internal(O)) : (0091 22) - 2576 7425
Office: EE-Annex BLDG.