S. Lodha

• CMOS process integration and device physics
• Materials and processes for advanced CMOS devices
• Metal-semiconductor interfaces
• Molecular devices

• Ph.D. Electrical Engineering, Purdue University, 2004
• M.S. Electrical and Computer Engineering, Purdue University, 2001
• B. Tech. Electrical Engineering, Indian Institute of Technology, Bombay 1999

• July 2010 - Present: Assistant Professor at Indian Institute of Technology, Bombay

• April 2010 - July 2010: Staff Engineer at Portland Technology Development, Intel Corporation. Led integrated efforts for developing a contact process for 22nm and 15nm technology nodes that meets transistor performance, reliability and yield targets.

• April 2005 - March 2010: Senior Process Integration Engineer at Portland Technology Development, Intel Corporation. Process integration engineer for development of 32nm and 45nm (industry first Hi-K/MG) logic technologies. Key contributions include development of gate patterning, replacement metal gate and silicide process modules meeting transistor performance, yield and reliability goals.

• S. Lodha, P. Ranade, C. Auth, “Method of forming CMOS transistors with dual metal silicide formed through the contact openings and structures formed thereby”, US Patent 7,861,406, 2011.

• U.Ganguly, S. Lodha, et al “Selector device for bipolar RRAM”, Indian Patent filed.

• V. Pavan Kishore, P. Paramahans, S. Sadana, U. Ganguly, and S. Lodha, “Nanocrystal-based Ohmic contacts on n and p-type germanium”, Appl. Phys. Lett. 100, 142107 (2012).
• P. D. Carpenter, S. Lodha, D. B. Janes, A. V. Walker, “Characterization of gold contacts in GaAs-based molecular devices: Relating structure to electrical properties”, Chem. Phys. Lett., 472, 220 (2009).
• S. Lodha and D. B. Janes, “Metal/Molecule/P-type GaAs Heterostructure Devices,” J. Appl. Phys. 100, 024503 (2006).
• S. Lodha, P. Carpenter and D. B. Janes, “Effect of Contact Properties on Current Transport in Metal/Molecule/GaAs Devices,” J. Appl.Phys. 99, 024510 (2006).
• S. Ghosh, H. Halimun, A. Mahapatro, J. Choi, S. Lodha and David Janes, “Device structure for electronic transport through individual molecules using nanoelectrodes,” Appl. Phys. Lett. 87, 233509 (2005).
• S. Lodha and David B. Janes, “Enhanced current densities in Au/molecule/GaAs devices,” Appl. Phys. Lett. 85, 2809 (2004).
• S. Lodha, David B. Janes and Nien-Po Chen, “Unpinned interface Fermi level in Schottky contacts to n-GaAs capped with low-temperature-grown GaAs; experiments and modeling using defect state distributions,” J. Appl. Phys. 93, 2772 (2003).
• S. Lodha, David B. Janes and Nien-Po Chen, “Fermi level unpinning in ex-situ Schottky contacts on n-GaAs capped with low-temperature-grown GaAs,” Appl. Phys. Lett. 80, 4452 (2002).

• P. Paramahans, S. Gupta, R. K. Mishra, N. Agarwal, A. Nainani, Y. Huang, M.C. Abraham, S. Kapadia, U. Ganguly, S. Lodha, “ZnO: an attractive option for n-type metal-interfacial layer-semiconductor (Si, Ge, SiC) contacts”, to appear at VLSI Symposium on Technology, Hawaii, 2012.
• P. Bafna, P. Karkare, S Srinivasan, S. Chopra, S. Lashkare, Y. Kim, S. Srinivasan, S. Kuppurao, S. Lodha, U. Ganguly, “4F2 Two-Terminal Selector for Bipolar RRAM: High on-current density and Random Dopant Fluctuation Effect”, to appear at Device Research Conference, Pittsburgh, 2012.
• S. Mittal, S. Gupta, A. Nainani, M.C. Abraham, K. Schuegraf, S. Lodha, U. Ganguly, “Epitaxialy defined (ED) FinFET: to reduce VT variability and enable multiple VT”, to appear at Device Research Conference, Pittsburgh, 2012.
• V. Pavan Kishore, P. Paramahans, S. Sadana, U. Ganguly, S. Lodha, “Contact Resistance Reduction on Germanium through Metal Work Function Engineering”, MRS Spring Meeting, San Francisco, 2012.
• P. Paramahans, P. Ray, S. Mane, P. Nyaupane, U. Ganguly, S. Lodha, “Ohmic contacts to n-type Germanium using a thin ZnO interfacial layer”, MRS Spring Meeting, San Francisco, 2012.
• V. Pavan Kishore, P. Paramahans, S. Sadana, U. Ganguly, S. Lodha, “Novel Nanocrystal-based Contacts on n and p-type Germanium”,39th Conference on the Physics and Chemistry of Surfaces and Interfaces (PCSI), Santa Fe, USA, January 2012.
• P. Packan, S. Akbar, M. Armstrong, D. Bergstrom, M. Brazier, H. Deshpande, K. Dev, G. Ding, T. Ghani,O. Golonzka, W. Han, J. He, R. Heussner, R. James, J. Jopling, C. Kenyon, S.-H. Lee, M. Liu, S. Lodha, B. Mattis, A. Murthy, L. Neiberg, J. Neirynck, S. Pae, C. Parker, L. Pipes, J. Sebastian, J. Seiple, B. Sell, A. Sharma, S. Sivakumar, B. Song, A. St. Amour, k. Tone, T. Troeger, C. Weber, K. Zhang, Y. Luo, S. Natarajan, “High performance 32nm logic technology featuring 2nd generation high-k + metal gate transistors”, International Electron Devices Meeting, Baltimore, MD, 2009.
• S. Natarajan, M. Armstrong; M. Bost., R. Brain, M. Brazier, C.-H. Chang, V. Chikarmane, M. Childs, H. Deshpande, K. Dev, G. Ding, T. Ghani, O. Golonzka, W. Han, J. He, R. Heussner,R. James, I. Jin, C. Kenyon, S. Klopcic, S.-H. Lee, M. Liu, S. Lodha, B. McFadden, A. Murthy, L. Neiberg, J. Neirynck, P. Packan, S. Pae, C. Parker, C. Pelto, L. Pipes, J. Sebastian, J. Seiple, B. Sell, S. Sivakumar, B. Song, K. Tone, T. Troeger, C. Weber, M. Yang, A. Yeoh, K. Zhang, “A 32nm logic technology featuring 2nd-generation high-k + metal-gate transistors, enhanced channel strain and 0.171?m2 SRAM cell size in a 291Mb array”, International Electron Devices Meeting, San Francisco, CA, 2008.
• P. Carpenter, A. Scott, S. Lodha, D. Janes, C. Risko, M. Ratner, “Substrate and Dipole Effects in Metal-Molecule-Semiconductor Heterostructures”, in Proceedings of the 6th IEEE conference on Nanotechnology, Cincinnati, 2006, vol. 1, pp. 104-107.
• S. Lodha and D. B. Janes, “Fabrication and electrical characterization of Au/molecule/GaAs devices,” in Proceedings of the 4th IEEE conference on Nanotechnology, Munich, 2004, pp. 278-80.

• D. B. Janes, S. Ghosh, S. Lodha, J. Choi and S. Bhattacharya, “Metal-Molecule-Metal and Metal-Molecule-Semiconductor Devices,” IEEE Nanoscale Devices and Systems Integration Conference, Miami, FL, Feb. 16-19, 2004.
• S. Lodha and D. B. Janes, “Metal-molecule-semiconductor heterostructures for nanoelectronic applications,” in Proceedings of the International Semiconductor Device Research Symposium, Washington D.C., 2003, pp. 446-7.
• J. Choi, D. Janes, H. Halimun, S. Lodha, et al., “Metal-Molecule-Metal Structures with Pre-Fabricated Contacts,” in Proceedings of the 4th International Conference on Intelligent Processing and Manufacturing of Materials, Sendai, Japan, May 18-23, 2003.
• S. Lodha, J. Choi, S. Bhattacharya and D. B. Janes, “Metal-molecule-semiconductor heterostructures for nano-device applications,” in Proceedings of the 3rd IEEE conference on Nanotechnology, San Francisco, Aug. 12-14, 2003, pp. 311-314.
• S. Bhattacharya, J. Choi, S. Lodha, D. B. Janes, A. Bonilla, K. Jeong and G. Lee, “Electronic Conduction in DNA attached to Gold Electrodes,” in Proceedings of the 3rd IEEE conference on Nanotechnology, San Francisco, Aug. 12-14, 2003, pp. 79-82.
• J. Choi, D. B. Janes, S. Lodha, Y. Chen, R. Agarwal, R. P. Andres, S. Burns and C. P. Kubiak, “Conduction through molecule-gold cluster complexes and applications,” in Proceedings of the 3rd IEEE conference on Nanotechnology, San Francisco, Aug. 12-14, 2003, pp. 164-167.
• D. B. Janes, S. Ghosh, J. Choi, S. Lodha and S. Bhattacharya, “Circuit characteristics of molecular electronic components,” in Proceedings of IEEE international conference on Application-Specific Systems, Architectures, and Processors, Netherlands, June 24-26, 2003, pp. 120-126.
• A.Topkar, S. Lodha and J. Vasi, “Ionizing radiation induced degradation of SiGe HBTs,” in Proceedings of the 10th Intl. Workshop on Physics of Semiconductor Devices, New Delhi, India, Dec. 1999, pp. 659-662.

Department of Electrical Engineering
IIT Bombay, Powai
Mumbai 400 076, India
Email : slodha[AT]ee.iitb.ac.in
Office room no: 606, Nanoelectronics Building