Souvik Mahapatra

souvik.jpg

Contact Information

Professor, Department of Electrical Engineering
IIT Bombay, Powai
Mumbai 400 076, India
Email: souvik@ee.iitb.ac.in
Email: mahapatra.souvik@gmail.com
Phone (Internal(O)): (0091 22) - 2576 7412
Fax: (0091 22) - 25723707
Office room no: 602, Nanoelectronics Building

PI, CEN IIT Bombay Phase 2 (2012-2016)
Convenor, IIT Bombay - Applied Materials Steering Committee

Google Scholar profile: http://scholar.google.co.in/citations?user=5j5CLuEAAAAJ

(Note: I do not offer summer internships)

Reliability Resources

Research Interests

  • Electrical characterization, modeling and simulation of micro/nano electronic devices
  • NBTI/PBTI and Hot carrier degradation in MOSFETs
  • High-k gate dielectrics
  • Advanced CMOS device reliability
  • Flash EEPROMs - Floating gate, SONOS/SANOS & Metal Nanoparticles
  • Solar cells

Academic Background

  • MSc (Physics), Jadavpur University, Calcutta, 1995
  • PhD (Electrical Engineering), IIT Bombay, 1999

Work Experience

  • PMTS, Bell Laboratories, Lucent Technologies, Murray Hill, NJ, USA (2000 - 2001)
  • Assistant Professor, Department of Electrical Engineering, IIT Bombay (2002 - 2004)
  • Associate Professor, Department of Electrical Engineering, IIT Bombay (2005 - 2008)
  • Visiting Faculty Fellow, Applied Materials, Santa Clara, CA, USA (June - December, 2006)
  • Professor, Department of Electrical Engineering, IIT Bombay (2009 - present)

Professional recognition and awards

Awards

Innovation Potential of Students Projects Award 2000 - Doctoral Level, Indian National Academy of Engineering (INAE), 2001, for research work done during Ph.D.

Young Engineer Award, Indian National Academy of Engineering (INAE), 2004, for early career research work done after joining IIT Bombay as an assistant professor.

Awarded Graduate Faculty appointment, School of Electrical Engineering and Computer Science, Purdue University, W. Lafayette, IN, USA (for the duration 2007 - 2016).

Awarded Tan Chin Tuan fellowship by Singapore government, to visit Nanyang Technological University, Singapore, 2008.

Fellow, Indian National Academy of Engineering (INAE), 2011.

Invited talks & tutorials in International conferences

Invited speaker, International Electron Devices Meeting (IEDM), San Francisco, USA, 2004.

Invited speaker, Insulating Films on Semiconductors (INFOS) Conference, IMEC, Lueven, Belgium, 2005.

Invited speaker, Solid State Devices & Materials (SSDM) Conference, Kobe, Japan, 2005.

Tutorial speaker, International Reliability Physics Symposium (IRPS), San Jose, CA, USA, 2006.

Tutorial speaker, International Reliability Physics Symposium (IRPS), Phoenix, AZ, USA, 2007.

Invited speaker, International Workshop on Physics of Semiconductor Devices (IWPSD), Mumbai, India, 2007.

Invited speaker, International Conference on Solid State and Integrated Circuit Technology (ICSICT), Beijing, China, 2008.

Invited speaker, VLSI conference, New Delhi, India, 2009.

Invited speaker, ECS spring meeting in San Francisco, CA, USA, 2009.

Invited speaker, ECS fall meeting in Vienna, Austria, 2009.

Tutorial speaker, International Reliability Physics Symposium (IRPS), Montreal, Canada, 2009.

Invited speaker, MIRAI Variability Conference, Tokyo, Japan, 2011.

Invited speaker, International Conference on Materials for Advanced Technologies (ICMAT), Singapore, 2011.

Tutorial speaker, International Conference on the Physical and Failure Analysis of Integrated Circuits (IPFA), Seuol, Korea, 2011.

Invited speaker, International Conference on the Physical and Failure Analysis of Integrated Circuits (IPFA), Seuol, Korea, 2011.

Invited speaker, Solid State Devices & Materials (SSDM) Conference, Nagoya, Japan, 2011.

Delivered IEEE DL lectures in the following IEEE-EDS Chapters: Santa Clara, New York, Singapore, Delhi, Bangalore

Delivered invited talks in the following Industries: Applied Materials (USA), IBM (USA), Micron Technologies (USA), Sun Microsystems (USA), SEMATECH (USA), Samsung (Korea), Global Foundries (Singapore), IMEC (Belgium), ST Microelectronics (France), Freescale Semiconductors (India), Moserbaer (India)

Delivered invited talks in the following Universities: UC Berkeley (USA), Stanford (USA), Purdue University (USA), TU (Vienna), Udine University (Italy), NUS and NTU (Singapore)

Standards

JEDEC standards document JEP122D, release October 2008, referred to the NBTI characterization, modeling and material dependence work.

Other professional recognition

Subcommittee member, International Reliability Physics Symposium (IRPS), San Jose, CA, USA, 2005, 2007-2011

Co-chair, transistor reliability committee, International Reliability Physics Symposium, Phoenix, AZ, USA, 2007

Technical program chair, 14th International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA), Bangalore, India 2007.

Chair, transistor reliability committee, International Reliability Physics Symposium, Anaheim, CA, USA, 2012

Senior member, IEEE.

Distinguished Lecturer (DL), IEEE Electron Devices Society.

Press coverage / Industry reports

EE-Times (January 2004) – covered work in the area of NBTI reliability.

Major international press including Nano world news, USA (April 2008) – covered work in the area of nitride based charge trap memory

Semiconductor memory strategies report, USA (March 2010) – covered work in the area of metal nanodot based charge trap memory.

Industrial collaboration

  • CHISEL NOR Flash (Hitachi, Japan)
  • SONOS NOR Flash (Renesas Technologies, Japan)
  • Metal Nanocrystal NAND Flash (Applied Materials, USA)
  • NBTI in SiON and Hi-K p-MOSFETs (Applied Materials, USA)
  • Advanced B4 NOR Flash (Genusion, Japan)
  • Reliability of ultrathin gate dielectrics (Renesas Technologies, Japan)
  • Optimization of Charge Trap Flash for NAND applications (Applied Materials, USA)
  • Split gate Flash EEPROM performance, scaling & reliability (TSMC, Taiwan, ROC)
  • High-k/MG for memory and logic applications (Applied Materials custom via SRC-GRC, USA)
  • Reliability of Flash memory tunnel oxide (Applied Materials, USA)
  • Devices for 3D memory applications (Micron Technologies, USA)
  • Modeling of Metal Nanocrystal Flash (Intel custom via SRC-GRC, USA)
  • Characterization of thin film solar cells (Applied Materials, USA)

Courses Offered

Theory

  • EE207 (Electronic Devices and Circuits)
  • EE432 (Special Semiconductor devices)
  • EE620 (Physics of Transistors)
  • EE661 (Physical Electronics)

Laboratory

  • EE219 (Electronics)
  • EE319 (Analog Circuits)
  • EE672 (Microelectronics)

Postgraduate thesis supervision

(In reverse chronological order)

Ph.D students graduated
  • Pawan K Singh (Metal Nanocrystal NAND Flash, 2010)
  • Sandhya C (Charge Trap NAND Flash, 2010)
  • Arnab Datta (2Bit SONOS NOR Flash, 2010)
  • Vrajesh Mehta (NBTI in SiON p-MOSFETs, 2009)
  • P Bharath Kumar (SONOS NOR Flash, 2007)
  • Deleep Nair (CHISEL NOR Flash, 2005)
Masters students graduated
  • Praneeth N S (NBTI in Hi-K/MG p-MOSFETs, 2010)
  • Mehul Thakkar (NBTI in Hi-K/MG p-MOSFETs, 2010)
  • Kshitij Auluck (Metal Nanocrystal NAND Flash, 2010)
  • Apoorva B Oak (SONOS NAND Flash, 2010)
  • Ameya Joshi (SONOS NAND Flash, 2010)
  • Suyog Gupta (SONOS NAND Flash, 2009)
  • Sakshi Bajaj (NBTI in SiON p-MOSFETs, 2009)
  • Nihit Chattar (SONOS NAND Flash, 2009)
  • Gaurav Bisht (Metal Nanocrystal NAND Flash, 2009)
  • Pankaj Shethi (B4 NOR Flash, 2009)
  • M Shivatheja (Metal Nanocrystal NAND Flash, 2009)
  • Hitesh Das (NBTI in SiON p-MOSFETs, 2008)
  • Mangesh Kushare (B4 NOR Flash, 2008)
  • Sambit Palit (SONOS NAND Flash, 2008)
  • Neeraj Goyal (NBTI in SiON p-MOSFETs, 2008)
  • Aneesh Nainani (Metal Nanocrystal Flash, 2007)
  • E Naresh Kumar (NBTI in SiON p-MOSFETs, 2007)
  • Shweta Purawat (NBTI in SiON p-MOSFETs, 2007)
  • Mohit Solanki (CMOS device reliability, 2007)
  • Sikha Rani (CMOS device reliability, 2007)
  • Leela Madhav (NBTI in SiON p-MOSFETs, 2006)
  • Sunny Gedam (SONOS NOR Flash, 2006)
  • Gaurav Gupta (NBTI in SiON p-MOSFETs, 2006)
  • Ch. Sridhar (SONOS NAND Flash, 2006)
  • Abhijeet Paul (SONOS NAND Flash, 2006)
  • Pawan K Singh (Metal Nanocrystal Flash, 2006)
  • Dhanoop Varghese (NBTI in SiON p-MOSFETs, 2005)
  • P. Bappana Naidu (SONOS NOR Flash, 2005)
  • Nitesh Jain (SONOS NAND Flash, 2005)
  • Siddharth Sharma (NBTI in SiON p-MOSFETs, 2005)
  • Dipankar Saha (CHC in CMOS devices, 2005)
  • K. Sridhar (SONOS NOR Flash, 2005)
  • Ravinder Sharma (SONOS NOR Flash, 2004)
  • Pradeep R. Nair (SONOS NOR Flash, 2004)
  • Tapas R. Dalei (NBTI in p-MOSFETs, 2004)
  • Anupama Garg (SONOS NOR Flash, 2004)
  • P Bharath Kumar (NBTI in p-MOSFETs, 2003)
  • Pankaj Pandhekar (CMOS device modeling, 2003)

Research overview

Has been individually working and supervising doctoral and master’s students in the areas of (a) Semiconductor device reliability - Negative Bias Temperature Instability (NBTI) and Hot Carrier Degradation (HCD) in SiO2, Si oxynitride (SiON), and high-k gate dielectric MOS devices, as well as (b) Flash nonvolatile memory (NVM) devices - conventional Floating Gate (FG) and SONOS for NOR type, metal nanocrystal and silicon nitride trap storage for NAND type applications.

Device reliability

Negative Bias Temperature Instability in Silicon Oxynitride (SiON) p-MOSFETs is a challenging reliability concern threatening IC qualification across the semiconductor IC industry. Designed novel experimental and analysis methodologies for NBTI study, identified and established strong SiON gate insulator process and material dependence of NBTI degradation. Developed novel stress and measurement methodologies and physics based models for lifetime determination. A brief overview follows:

Characterization protocols: Demonstrated the existence of maximum allowable bias limit during accelerated stress tests, to prevent long-time measured data from being corrupted by additional, non NBTI related trap generation. Established the robustness of power-law time dependence of degraded MOSFET parameters under a wide range of stress conditions, by using delay-free characterization to prevent power law time exponent contamination. This standardization facilitated reliable determination of extrapolated lifetime.

Material dependence: Demonstrated influence of gate dielectric Nitrogen (N) distribution profile on NBTI time, temperature and bias dependent parameters. Correlated NBTI parameters to wide range of SiON processes, i.e., Rapid Thermal Nitrided Oxide (RTNO), Plasma Nitrided Oxide (PNO) with different Equivalent Oxide Thickness (EOT), N dose, Post Nitridation Anneal (PNA). Established PNO SiON with proper PNA being essential to reduce Si/SiON interfacial N density and keep NBTI under acceptable limits.

Physics and modeling: Demonstrated NBTI correlation to inversion layer holes and oxide field, and developed physics-based field acceleration models for extrapolation of stress data to use conditions. Demonstrated self-consistent methodology to isolate hole trapping and interface trap generation components of NBTI degradation, essential for predicting extrapolated degradation, and established their gate insulator material dependence. Demonstrated interface trap generation dominates NBTI for well-optimized devices, and developed time evolution models to extrapolate stress data to end-of-life.

In addition, also explored BTI and hot carrier co-degradation issues in MOS devices, and developed universal degradation mechanisms governing the reliability of MOS gate insulators. Developed a novel charge pumping technique to determine the spatial distribution profile interface and oxide damage distributions after hot carrier stressing in MOSFETs. Studied hot carrier stress induced damage distribution under a wide range of stress conditions using the proposed CP technique in conventional, channel engineered and high-k MOSFETs. Use TCAD device simulation to explain the experimentally obtained damage distribution. Presently working on BTI reliability of high-k/metal gate MOS gate stacks for sub 22nm logic nodes.

Flash NVM

These semiconductor devices are used in portable consumer electronics for code and data storage. Has worked on a wide range of such nonvolatile memory devices for NOR and NAND applications. The brief overview follows:

CHISEL Flash: Designed scaled FG cell under NOR architecture using process, device and Monte Carlo simulation (optimization of channel and S/D junction). Performed electrical characterization of fabricated devices to evaluate performance and reliability, understanding the physics and scalability of channel initiated secondary impact ionization (CHISEL) process and related reliability mechanisms (window closure during write-erase cycling, drain disturb before and after cycling).

SONOS NOR Flash EEPROMs: Performed electrical characterization, modeling and simulation of localized write and erase for 1 bit/cell and 2 bit/cell memory operation in silicon nitride storage based cells under NOR architecture. Established the impact of channel engineering on performance and reliability (window closure during cycling endurance, read and drain disturb, as well as bit coupling under 2bit/cell operation), and evaluated localized charge distribution after write and loss mechanism during retention bake.

Beyond FG NAND Flash EEPROMs: Performed fabrication, electrical characterization, modeling and simulation, including development of physics-based simulators to explore performance and reliability of (a) metal nanocrystal and (b) silicon nitride based storage memory devices for NAND data storage applications. Established that gate dielectric stacks with metal nanodots pose no fundamental reliability concern as far as memory application is concerned. Determined performance and reliability for different metal nanodot configurations (single versus dual layers, metal type, dot diameter and density, area coverage etc.). Established silicon nitride composition impact on CTF memory performance (memory window, speed) and reliability (cycling endurance and data retention). Presently working on finalizing in house simulator software for both metal nanodot and nitride based CTF memory.

CHISEL NOR Flash EEPROMs: Played a key role in developing CHISEL (Channel Initiated Secondary Electron) Flash cells in 0.18m technology. Primary responsibilities involved unit cell design (optimization of channel and junction structures) using process, device and Monte Carlo simulations, electrical characterization of fabricated devices for performance and reliability benchmarking, and interaction with process teams for cell design optimization. Also went on to work on understanding the physics and scalability of CHISEL process for scaled nodes, including programming efficiencies and related reliability mechanisms (window closure during write-erase cycling, drain disturb and data retention before and after cycling). This leading role had enabled world’s first commercialization of CHISEL Flash by Hitachi Ltd., Japan (2001), under the Lucent-Hitachi JDA, for 32Mb and 64Mb products for standalone NOR applications. It is believed that most NOR Flash products today use CHISEL mechanism during programming operation.

List of Publications

(Subdivided into research topics, and in reverse chronological order)

Area: Negative Bias Temperature Instability (NBTI)

Journals

S. Deora, A. E. Islam, M. A. Alam and S. Mahapatra, “A common framework of NBTI generation and recovery in plasma nitrided SiON p-MOSFETs”, IEEE Electron Dev. Lett., v.30, p.978, 2009.

S. Mahapatra, V. D. Maheta, A. E. Islam and M. Alam, “Isolation of NBTI stress generated interface trap and hole trapping components in PNO p-MOSFETs”, IEEE Trans. Electron Devices, v.56, p.236, 2009.

S. Deora, V. D. Maheta, G. Bersuker, C. Olsen, K. Ahmed, R. Jammy and S. Mahapatra, “A comparative NBTI study of HfO2, HfSiOX and SiON p-MOSFETs using UF-OTF IDLIN technique”, IEEE Electron Dev. Lett., v.30, p.152, 2009.

V. D. Maheta, E. N. Kumar, S. Purawat, C. Olsen, K. Ahmed and S. Mahapatra, “Development of an ultra-fast on-the-fly IDLIN technique to study NBTI in plasma and thermal oxynitride p-MOSFETs”, IEEE Trans. Electron Devices, v.55, p.2614, 2008.

V. D. Maheta, C. Olsen, K. Ahmed and S. Mahapatra, “The impact of nitrogen engineering in silicon oxynitride gate dielectric on negative bias temperature instability in p-MOSFETs: A study by ultra-fast on-the-fly IDLIN technique”, IEEE Trans. Electron Devices, v.55, p.1630, 2008.

A. E. Islam, G. Gupta, K. Z. Ahmed, S. Mahapatra and M. A. Alam, “Optimization of gate leakage and NBTI for plasma-nitrided gate oxides by numerical and analytical models”, IEEE Trans. Electron Devices, v.55, p.1143, 2008.

(Invited) S. Mahapatra and M. A. Alam, “Defect generation in p-MOSFETs under negative bias stress: An experimental perspective”, IEEE Trans. Materials and Dev. Reliability, v.8, p.35, 2008.

D. Varghese, G. Gupta, L. Madhav, D. Saha, K. Ahmed, F. Nouri and S. Mahapatra, “Physical Mechanism and Gate Insulator Material Dependence of Generation and Recovery of Negative Bias Temperature Instability in p-MOSFETs”, IEEE Trans. Electron Devices, p.1672, v.54, July 2007.

(Invited) A. E. Islam, H. Kufluoglu, D. Varghese, S. Mahapatra and M. A. Alam, “Recent issues in negative bias temperature instability: Initial degradation, field dependence of interface trap generation, hole trapping effects and relaxation”, IEEE Trans. Electron Devices, p.2143, v.54, September, 2007.

M. A. Alam, H. Kufluoglu, D. Varghese and S. Mahapatra, “A Comprehensive Model of PMOS NBTI Degradation: Recent progress”, Microelectronics Reliability, v.47, p.853, 2007.

(Invited) M. A. Alam and S. Mahapatra, “A Comprehensive Model of PMOS NBTI Degradation”, Microelectronics Reliability, special issue on NBTI, v.45, p.71, 2005

D. Varghese, S. Mahapatra and M. A. Alam, “Hole energy dependent interface trap generation in MOSFET Si/SiO2 interface”, IEEE Electron Devices Lett., v.26, p.572, Aug. 2005.

S. Mahapatra, P. Bharath Kumar and M. A. Alam, “Investigation and Modeling of Interface and Bulk Trap Generation During Negative Bias Temperature Instability of p-MOSFETs”, IEEE Trans. Electron Devices, v.51, p.1371, 2004.

Conferences

S. Deora, V. D. Maheta, and S. Mahapatra, “NBTI lifetime prediction in SiON p-MOSFETs by H/H2 reaction diffusion (RD) and dispersive hole trapping model”, in Proc., Int. Rel. Phys. Symp (IRPS), Anaheim, CA, USA,, p.1105, 2010.

A. E. Islam, S. Mahapatra, S. Deora, V. D. Maheta and M. A. Alam, “On the differences between ultra-fast NBTI measurements and reaction diffusion theory”, in Proc., IEEE Int. Elect. Dev. Meet. (IEDM), Baltimore, MD, USA, 2009.

(Invited) S. Mahapatra, V. D. Maheta, S. Deora, E. N. Kumar, S. Purawat, C. Olsen, K. Ahmed, A. E. Islam and M. A. Alam, “Material dependence of negative bias temperature instability (NBTI) stress and recovery in SiON p-MOSFETs”, ECS meeting, San Francisco, CA, USA, 2009.

G. Kapila, N. Goyal, V. D. Maheta, C. Olsen, K. Ahmed and S. Mahapatra, “A comprehensive study of flicker noise in plasma nitrided SiON p-MOSFETs: Process dependence of pre-existing and NBTI stress generated trap distribution profiles”, in Proc., IEEE Int. Elect. Dev. Meet. (IEDM), San Francisco, CA, USA, 2008.

(Invited) S. Mahapatra and V. D. Maheta, “Gate insulator process dependent NBTI in SiON p-MOSFETs”, in Proc., Int. Conf. on Solid State and Integrated Circuit Technology (ICSICT), Beijing, China, 2008.

S. Deora and S. Mahapatra, “A study of NBTI in HfSiON/TiN p-MOSFETs using ultra-fast on-the-fly IDLIN technique”, Int. Phys. Failure Analysis conf., Singapore 2008.

S. Mahapatra, K. Ahmed, D. Varghese, A. E. Islam, G. Gupta, L. Madhav, D. Saha and M. A. Alam, “On the Physical Mechanism of NBTI in Silicon Oxynitride p-MOSFETs: Can Differences in Insulator Processing Conditions Resolve the Interface Trap Generation versus Hole Trapping Controversy?”, in Proc., Int. Rel. Phys. Symp (IRPS), Phoenix, AZ, USA, p.1, April 2007.

A.E. Islam, E. N. Kumar, H. Das, S. Purawat, V. Maheta, H. Aono, E. Murakami, S. Mahapatra, and M.A. Alam, “Theory and Practice of Ultra-fast Measurements for NBTI Degradation: Challenges and Opportunities”, Int. Electron Dev. Meet. (IEDM), Washington DC, USA, Dec 2007.

E. N. Kumar, V. D. Maheta, S. Purawat, A. E. Islam, C. Olsen, K. Ahmed, M. A. Alam and S. Mahapatra, “Material Dependence of NBTI Physical Mechanism in Silicon Oxynitride (SiON) p-MOSFETs: A Comprehensive Study by Ultra-Fast On-The-Fly (UF-OTF) IDLIN Technique”, Int. Elect. Dev. Meet. (IEDM), Washington DC, USA, Dec 2007.

A. E. Islam, G. Gupta, S. Mahapatra, A. T. Krishnan, K. Ahmed, F. Nouri, A. Oates and M. A. Alam, “Gate leakage vs. NBTI in plasma nitrided oxides: Characterization, physical principles and optimization”, International Electron Devices Meeting (IEDM), San Francisco, CA, USA, p.403, 2006.

P. Bharath Kumar, T. R. Dalei, D. Varghese, D. Saha, S. Mahapatra and M. A. Alam, “Impact of Substrate Bias on p-MOSFET Negative Bias Temperature Instability”, Int. Reliability Phys. Symp (IRPS), San Jose, USA, p.700, 2005.

(Invited) S. Mahapatra, M. A. Alam, P. Bharath Kumar, T. R. Dalei, D. Varghese and D. Saha, “Negative bias temperature instability in CMOS devices”, Microelectronics Engineering, special issue on INFOS, v.80, p.114, 2005.

D. Varghese, D. Saha, S. Mahapatra, K. Ahmed, F. Nouri and M. Alam, “On the dispersive versus arrhenius temperature activation of NBTI time evolution in plasma nitrided gate oxides: Measurements, theory and implications”, International Electron Devices Meeting (IEDM), Washington, DC, USA, p.684, Dec 2005.

(Invited) S. Mahapatra, M. A. Alam, P. Bharath Kumar, T. R. Dalei and D. Saha, “Mechanism of Negative Bias Temperature Instability in CMOS Devices: Degradation, Recovery and Impact of Nitrogen”, International Electron Devices Meeting (IEDM), San Francisco, CA, USA, p.105, 2004.

S. Mahapatra, P. Bharath Kumar and M. A. Alam, “A new observation of enhanced bias temperature instability in thin gate oxide p-MOSFET”, Tech. Digest, International Electron Devices Meeting (IEDM), Washington, DC, USA, p.337, 2003.

S. Mahapatra and M. A. Alam, “A predictive reliability model for PMOS bias temperature degradation”, Tech. Digest, International Electron Devices Meeting (IEDM), San Francisco, CA, USA, p.505, 2002.

Area: Beyond Floating Gate NAND Flash memory

Journals

P. K. Singh, G, Bisht, K. Auluck, M. Shivatheja, R. Hofmann, K. K. Singh and S. Mahapatra, “Performance and reliability study of single layer and dual layer Platinum nanocrystal Flash memory devices under NAND operation”, to appear, IEEE Trans. Electron Devices, 2010.

C. Sandhya, A. B. Oak, N. Chattar, U. Ganguly, C. Olsen, S. M. Seutter, L. Date, R. Hung, J. Vasi and S. Mahapatra, “Study of P/E cycling endurance induced degradation in SANOS memories under NAND (FN/FN) operation”, IEEE Trans. Electron Devices, v.57, p.1548, 2010.

C. Sandhya, A. B. Oak, N. Chattar, A. S. Joshi, U. Ganguly, C. Olsen, S. M. Seutter, L. Date, R. Hung, J. Vasi and S. Mahapatra, “Impact of SiN composition variation on SANOS memory performance and reliability under NAND (FN/FN) operation”, IEEE Trans. Electron Devices, v.56, p.3123, 2009.

P. K. Singh, R. Hofmann, G. Bisht, K. K. Singh, N. Krishna and S. Mahapatra, “Performance and reliability of Au and Pt single layer metal nanocrystal flash memory under NAND (FN/FN) operation”, IEEE Trans. Electron Devices, v.56, p.2065, 2009.

C. Sandhya, U. Ganguly, N. Chattar, C. Olsen, S. M. Seutter, L. Date, R. Hung, J. Vasi and S. Mahapatra, “Effect of SiN on performance and reliability of charge trap flash (CTF) under Fowler-Nordheim tunneling program/erase operation”, IEEE Electron Dev. Lett., v.30, p.171, 2009.

P. K. Singh, G. Bisht, R. Hofmann, K. Singh, N. Krishna, and S. Mahapatra, “Metal nanocrystal memory with Pt single and dual layer NC with low leakage Al2O3 blocking dielectric”, IEEE Electron Dev. Lett., v.29, p.1389, 2008.

Conferences

P. Singh, C. Sandhya, K. Auluck, G. Bisht, M. Shivatheja, R. Hofmann, G. Mukhopadhyay and S. Mahapatra, “Applicability of dual layer metal nanocrystal flash memory for NAND 2 or 3-bit/cell operation: Understanding the anomalous breakdown and optimization of P/E conditions”, in Proc., Int. Rel. Phys. Symp, p.981, Anaheim, USA, p.981, 2010.

Z. Z. Lwin, K. L. Pey, Y. N. Chen, P. K. Singh and S. Mahapatra, “Charging and discharging characteristics of metal nanocrystals in degraded dielectric stack”, in Proc., Int. Rel. Phys. Symp, p.981, Anaheim, USA, p.89, 2010.

(Invited) S. Mahapatra and P. K. Singh, “Metal/high-k/metal nanocrystal gate stacks for NAND flash applications”, ECS meeting, Vienna, Austia, 2009.

P. K. Singh, G. Bisht, M. Sivatheja, C. Sandhya, R. Hofmann, K. Singh, N. Krishna, G. Mukhopadhyay, and S. Mahapatra, “Reliability of SL and DL Pt NC devices for NAND Flash applications: A 2 region model for endurance defect generation”, in Proc., Int. Rel. Phys. Symp, p. 301, Montreal, Canada, 2009.

P. K. Singh, G. Bisht, R. Hofmann, K. Singh and S. Mahapatra, “Dual layer Pt metal NC Flash for MLC NAND application”, in Proc., Int. Memory Workshop, p. 78, Monterey, CA, USA, 2009.

P. K. Singh, K. K. Singh, R. Hofmann, K. Armstrong, N. Krishna and S. Mahapatra, “Au nanocrystal flash memory reliability and failure analysis”, Int. Phys. Failure Analysis conf., Singapore 2008.

Sandhya C, U. Ganguly, K.K. Singh, C. Olsen, S. M. Seutter, G. Conti, K. Ahmed, N. Krishna, J. Vasi and S. Mahapatra, “The Effect of Band Gap Engineering of the Nitride Storage Node on Performance and Reliability of Charge Trap Flash”, Int. Phys. Failure Analysis conf., Singapore 2008.

Sandhya C, U. Ganguly, K.K. Singh, P.K. Singh, C. Olsen, S. M. Seutter, R. Hung, G. Conti, K. Ahmed, N. Krishna, J. Vasi, and S. Mahapatra, “Nitride engineering and the effect of interfaces on charge trap flash performance and reliability”, Int. Rel. Phys. Symp. (IRPS), Phoenix, AZ, USA 2008.

A. Nainani, S. Palit, P. K. Singh, U. Ganguly, N. Krishna, J. Vasi and S. Mahapatra, “Development of A 3D Simulator for Metal Nanocrystal (NC) Flash Memories under NAND Operation”, Int. Elect. Dev. Meet. (IEDM), Washington DC, USA, Dec 2007.

A. Paul, Ch. Sridhar, S. Gedam and S. Mahapatra, “Comprehensive simulation of program, erase and retention in charge trapping flash memories”, International Electron Devices Meeting (IEDM), San Francisco, CA, USA, p.393, Dec 2006.

Area: SONOS NOR Flash memory

Journals

A. Datta and S. Mahapatra, “A comprehensive analysis on scaling prospects of dual-bit channel engineered SONOS NOR-flash EEPROM cells”, Solid State Electron., v.54, p.397, 2010.

A. Datta, R. Asnani and S. Mahapatra, “A novel gate assisted reverse read scheme to control bit coupling and read disturb for multibit/cell operation in deeply scaled split-gate SONOS flash EEPROM cells”, IEEE Electron Dev. Lett., v.30, p.885, 2009.

P. Bharath Kumar, R. Sharma, P. R. Nair and S. Mahapatra, “Investigation of drain disturb in SONOS Flash EEPROMs”, IEEE Trans. Electron Devices, v.54, p.98, 2007.

A. Datta, P. Bharath Kumar and S. Mahapatra, “Dual-bit/Cell SONOS Flash EEPROMs: Impact of Channel Engineering on Programming Speed and Bit Coupling Effect”, IEEE Electron Dev. Lett., p.446, v.28, 2007.

P. Bharath Kumar, D. Nair and S. Mahapatra, “Using Soft Secondary Electron Programming to reduce Drain Disturb in Floating Gate NOR Flash EEPROMs”, IEEE Trans. Device and Materials Reliability, v.6, p.81, 2006.

P. Bharath Kumar, P. R. Nair, R. Sharma, S. Kamohara and S. Mahapatra, “Lateral profiling of trapped charge in SONOS Flash EEPROMs programmed using channel hot electron injection”, IEEE Trans. Electron Devices, v.53, p.698, 2006.

Conferences

P. Bharath Kumar, E. Murakami, S. Kamohara, and S. Mahapatra, “Endurance and Retention Characteristics of SONOS EEPROMs operated using BTBT Induced Hot Hole Erase”, Int. Reliability Phys. Symp (IRPS), San Jose, USA, p., 2006.

P. Bharath Kumar, Ravinder Sharma, Pradeep R. Nair, Deleep R. Nair, S. Kamohara, S. Mahapatra, and J. Vasi, “Mechanism of drain disturb in SONOS Flash EEPROMs”, Int. Reliability Phys. Symp (IRPS), San Jose, USA, p.186, 2005.

P. Bharath Kumar, D. R. Nair, and S. Mahapatra, “Soft Secondary Electron Programming for Floating Gate NOR Flash EEPROMs”, International Symposium on the Physical and Failure Analysis of Integrated Circuits, Singapore, p.146, 2005.

K. Sridhar, P. Bharath Kumar, S. Mahapatra, E. Murakami , and S. Kamohara, “Controlling Injected Electron and Hole Profiles for Better Reliability of Split Gate SONOS “, International Symposium on the Physical and Failure Analysis of Integrated Circuits, Singapore, p.190, 2005.

P. Bharath Kumar, Ravinder Sharma, E. Murakami , S. Kamohara, and S. Mahapatra, “Effect of Compensation Implant in SONOS Flash EEPROMs”, International Conference on Solid State Devices and Materials (SSDM), Tokyo, Japan, p.644, 2005.

P. R. Nair, P. Bharath Kumar, R. Sharma, S. Kamohara and S. Mahapatra, “A Comprehensive Trapped Charge Profiling Technique for SONOS Flash EEPROMs”, Proceedings, International Electron Devices Meeting (IEDM), San Francisco, CA, USA, p.403, 2004.

Area: CHISEL NOR Flash memory

Journals

D. R. Nair, S. Mahapatra, S. Shukuri and J. Bude, “Explanation of P/E Cycling Impact on Drain Disturb in Flash EEPROMs under CHE and CHISEL Programming Operation”, IEEE Trans. Electron Devices, v.52, p.534, 2005.

D. R. Nair, N. R. Mohapatra, S. Mahapatra, S. Shukuri and J. Bude, “Effect of P/E cycling on drain disturb in Flash EEPROMs under CHE and CHISEL operation”, IEEE Trans. Device and Materials Reliability, v.4, p.32, 2004.

D. R. Nair, S. Mahapatra, S. Shukuri and J. Bude, “Drain disturb during CHISEL programming of NOR Flash EEPROMs – Physical mechanisms and impact of technological parameters”, IEEE Trans. Electron Devices, v.51, p.701, 2004.

D. R. Nair, S. Mahapatra and S. Shukuri, “Cycling endurance of NOR Flash EEPROM cells under CHISEL programming operation - Impact of technological parameters and scaling”, IEEE Trans. Electron Devices, v.51, p.1672, 2004.

N. R. Mohapatra, D. R. Nair, S. Mahapatra, V. R. Rao, S. Shukuri and J. Bude, “CHISEL programming operation of scaled NOR Flash EEPROMs – Effect of voltage scaling, device scaling and technological parameters”, IEEE Trans. Electron Devices, v.50, p.2104, 2003.

S. Mahapatra, S. Shukuri and J. Bude, “CHISEL flash EEPROM part-I: performance and scaling”, IEEE Trans. Electron Devices, v.49, p.1296, 2002.

S. Mahapatra, S. Shukuri and J. Bude, “CHISEL flash EEPROM part-II: reliability”, IEEE Trans. Electron Devices, v.49, p.1302, 2002.

Conferences

D. R. Nair, S. Mahapatra, S. Shukuri and J. Bude, “Multi-Level Programming of NOR Flash EEPROMs by CHISEL Mechanism”, Proceedings, Int. Reliability Phys. Symp (IRPS), Phoenix, USA, p.635, 2004.

S. Mahapatra, S. Shukuri and J. Bude, “Substrate bias effect on cycling induced performance degradation of scaled flash EEPROMs”, Proceedings, 16th IEEE VLSI Design Conference, New Delhi, India, p.223, 2003.

N. R. Mohapatra, S. Mahapatra, V. R. Rao, S. Shukuri and J. Bude, “Effect of programming biases on the reliability of CHE and CHISEL flash EEPROMs”, Proceedings, Int. Reliability Phys. Symp (IRPS), Dallas, USA, p.518, 2003.

D. R. Nair, N. R. Mohapatra, S. Mahapatra, S. Shukuri and J. Bude, “The effect of CHE and CHISEL programming operation on drain disturb in flash EEPROMs”, Proceedings, 10th International Symposium on the Physical and Failure Analysis of Integrated Circuits, Singapore, p.164, 2003.

N. R. Mohapatra, D. R. Nair, S. Mahapatra, V. R. Rao and S. Shukuri, “The Impact of Channel Engineering on the Performance Reliability and Scaling of CHISEL NOR Flash EEPROMs”, Proceedings, 33rd European Solid State Device Research Conference (ESSDERC), Lisbon, Portugal, p.541, 2003.

D. R. Nair, N. R. Mohapatra, S. Mahapatra and S. Shukuri, “The Impact of Technology Parameters and Scaling on the Programming Performance and Drain Disturb in CHISEL Flash EEPROMs”, Proceedings, International Conference on Solid State Devices and Materials (SSDM), Tokyo, Japan, p.644, 2003.

N. R. Mohapatra, S. Mahapatra and V. R. Rao, “Device Scaling Effects on Substrate Enhanced Degradation in MOS Transistors”, 2002 MRS Spring Meeting, San Francisco, CA, USA, April 1-5, 2002.

S. Mahapatra, S. Shukuri and J. Bude, “Performance and reliability of high-density flash EEPROMs under CHISEL programming operation”, Proceedings, 32nd European Solid-State Device Research Conference (ESSDERC), Florence, Italy, p., 2002.

Area: Channel Hot Carrier (CHC) Degradation

Journals

D. Saha, D. Varghese and S. Mahapatra, “On the Generation and Recovery of Hot Carrier Induced Interface Traps: A critical examination of the 2D Reaction Diffusion model”, IEEE Electron Devices Lett., v.27, p.188, 2006.

D. Saha, D. Varghese and S. Mahapatra, “The role of Anode Hole Injection and Valence Band Hole Tunneling on interface trap generation during hot carrier injection stress”, IEEE Electron Devices Lett., p.585, 2006.

S. Mahapatra, D. Saha, D. Varghese and P. Bharath Kumar, “On the generation and recovery of interface traps in MOSFETs subjected to NBTI, FN and HCI stress”, IEEE Trans. Electron Devices, p.1583, 2006.

K. G. Anil, S. Mahapatra and I. Eisele, “A detailed experimental investigation of impact ionization in n-channel metal-oxide-semiconductor field-effect-transistors at very low drain voltages”, Solid State Electron, v.47, p.995, 2003.

K. G. Anil, S. Mahapatra and I. Eisele, “Electron-electron interaction signature peak in the substrate current vs gate voltage characteristics of n-channel silicon MOSFETs”, IEEE Trans. Electron Devices v.49, p.1283, 2002.

K. G. Anil, S. Mahapatra, V. R. Rao and I. Eisele, “Comparison of sub-bandgap impact ionization in deep-submicron conventional and lateral asymmetric channel n-MOSFETs”, Jpn. J. Appl. Phys., v.40, p-I, no.4B, p.2621, April 2001.

K. G. Anil, S. Mahapatra and I. Eisele, “Observation of double peak in the substrate current versus gate voltage characteristics in n-channel MOSFETs”, Appl. Phys. Lett., v.78, no.15, p.2238, April 2001.

K. G. Anil, S. Mahapatra and I. Eisele, “Experimental verification of the nature of the high energy tail in the electron energy distribution in n-channel MOSFETs”, IEEE Electron Devices Lett., v.22, p.478, Oct. 2001.

S. Mahapatra, V. R. Rao, B. Cheng, M. Khare, C. D. Parikh, J. C. S. Woo and J. Vasi, “Performance and Hot-Carrier Reliability of 100 nm Channel Length Jet Vapor Deposited Si3N4 MNSFETs”, IEEE Trans. Electron Devices, v.48, p.679, April 2001.

S. Mahapatra, V. R. Rao, C. D. Parikh, J. Vasi, B. Cheng and J. C. S. Woo, “A study of hot-carrier induced interface trap profiles in lateral asymmetric channel MOSFETs using a novel charge pumping technique”, Solid State Electron, v.45, p.1717, 2001.

S. Mahapatra, C. D. Parikh, V. R. Rao, C. R. Viswanathan and J. Vasi, “A comprehensive study of hot-carrier induced interface and oxide trap distributions in MOSFETs using a novel charge pumping technique”, IEEE Trans. Electron Devices, v.47, p.171, Jan 2000.

S. Mahapatra, C. D. Parikh, V. R. Rao, C. R. Viswanathan and J. Vasi, “Device scaling effects on hot-carrier induced interface and oxide trapped charge distributions in MOSFETs”, IEEE Trans. Electron Devices, v.47, p.789, April 2000.

S. Mahapatra, V. R. Rao, C. D. Parikh, J. Vasi, B. Cheng and J. C. S. Woo, “A study of 100 nm channel length asymmetric channel MOSFET by using charge pumping”, Microelectronics Engineering, v.48, p.193, Sept 1999.

S. Mahapatra, C. D. Parikh, J. Vasi, V. R. Rao and C. R. Viswanathan, “A direct charge pumping technique for spatial profiling of hot-carrier induced interface and oxide traps in MOSFETs”, Solid State Electron, v.43, p.913, June 1999.

S. Mahapatra, C. D. Parikh and J. Vasi, “A new ‘multifrequency’ charge pumping technique to profile hot-carrier induced interface-state density in n-MOSFETs”, IEEE Trans. Electron Devices, v.46, p.960, May 1999.

Conferences

N. R. Mohapatra, S. Mahapatra and V. R. Rao, “The study of damage generation in n-channel MOS transistors operating in the substrate enhanced gate current regime”, Proceedings, 9th International Symposium on the Physical and Failure Analysis of Integrated Circuits, Singapore, p. 27, 2002.

N. R. Mohapatra, S. Mahapatra, V. R. Rao, “”Study of Degradation in Channel Initiated Secondary Electron Injection Regime”, Proceedings, 31st European Solid-State Device Research Conference (ESSDERC), 11 - 13 September 2001, Nuremberg, Germany, p. 2001.

N. R. Mohapatra, S. Mahapatra and V. R. Rao, “A Comparative Study of Degradation for n-MOSFET’s in CHE and CHISEL Injection Regime”, Proceedings, 11th International Workshop on The Physics of Semiconductor Devices, New Delhi, India, p., 2001

G. Shrivastav, S. Mahapatra, V. R. Rao, J. Vasi, K. G. Anil, C. Fink, W. Hansch and I. Eisele, “Performance Optimization of 60 nm Channel Length Vertical MOSFETs Using Channel Engineering”, Proceedings, 14th IEEE VLSI Design Conference, Bangalore, India, p.475, 2001.

Anil K. G., S. Mahapatra and I. Eisele, “Role of inversion layer quantization on sub-bandgap impact ionization in deep-sub-micron n-channel MOSFETs”, Tech. Digest, International Electron Devices Meeting (IEDM), San Francisco, CA, USA, p.675, 2000.

S. Mahapatra, V. R. Rao, J. Vasi, B. Cheng, and J.C.S. Woo, “Reliability Studies on Sub 100 nm SOI-MNSFETs”, International Integrated Reliability Workshop (IRW), Stanford, CA, USA, 2000.

V. R. Rao, S. Mahapatra, J. Vasi, K. G. Anil, C. Fink, W. Hansch and I. Eisele, “Hot-carrier performance of 60 nm channel length delta-doped vertical MOSFETs with high-pressure grown oxide as a gate dielectric”, 30th IEEE Semiconductor Interface Specialists Conference (SISC), San Diego, California, USA, 2000.

Anil K. G., S. Mahapatra, I. Eisele, V. R. Rao and J. Vasi, “Drain bias dependence of gate oxide reliability in conventional and asymmetrical channel MOSFETs in the low voltage regime”, Proceedings, 30th European Solid State Device Research Conference (ESSDERC), Cork, Ireland, p.124, 2000.

S. Mahapatra, V. R. Rao, K. N. ManjulaRani, C. D. Parikh, J. Vasi, B. Cheng, M. Khare and J. C. S. Woo, “100 nm channel length MNSFETs using a Jet Vapor Deposited ultra-thin silicon nitride gate dielectric”, Tech. Digest, International Symposium on VLSI Technology, Kyoto, Japan, p.79, 1999.

S. Mahapatra, V. R. Rao, C. D. Parikh, J. Vasi, B. Cheng, M. Khare and J. C. S. Woo, “Hot-carrier induced interface degradation in Jet Vapor Deposited SiN MNSFETs as studied by a novel charge pumping technique”, Proceedings, 29th European Solid State Device Research Conference (ESSDERC), Leuven, Belgium, p.592, 1999.

S. Mahapatra, K. N. ManjulaRani, V. R. Rao and J. Vasi, ‘ULSI MOS transistors with Jet Vapor Deposited (JVD) silicon nitride for the gate insulator”, Proceedings, 10th International Workshop on Physics of Semiconductor Devices (IWPSD), New Delhi, India, p., 1999.

S. Mahapatra, V. R. Rao, C. D. Parikh, J. Vasi, B. Cheng and J. C. S. Woo, “Hot-carrier induced interface trap distributions in conventional and asymmetric channel MOSFETs as determined by a novel charge pumping technique”, 29th IEEE Semiconductor Interface Specialists Conf. (SISC), South Carolina, USA, 1999.

S. Mahapatra, C. D. Parikh and J. Vasi, “A reliable approach to determine hot-carrier induced interface state distribution in n-MOSFET using charge pumping”, Proceedings, International Conference on Computers and Devices for Communication (CODEC), Calcutta, India, p. 373, 1998.

S. Mahapatra, C. D. Parikh and J. Vasi, “A new technique to profile hot-carrier induced interface-state generation in n-MOSFETs using charge pumping”, Proceedings, 9th International Workshop on Physics of Semiconductor Devices (IWPSD), New Delhi, India, p. 1030, 1997.

 
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