Souvik Mahapatra

• Flash EEPROMs - Floating gate, SONOS & Nanoparticle
• NBTI and Hot carrier degradation in MOSFETs
• High-k gate dielectrics
• Advanced CMOS device reliability

• EE207 Electronic Devices and Circuits
• EE432 Special Semiconductor devices
• EE620 Physics of Transistors
• EE661 Physical Electronics

• EE219 Electronics
• EE319 Analog Circuits
• EE672 Microelectronics

• MSc (Physics), Jadavpur University, Calcutta, 1995
• PhD (Electrical Engineering), IIT Bombay, 1999

• Professor, Department of Electrical Engineering, IIT Bombay (present)
• Tan Chin Tuan Fellow, Nanyang Technological University, Singapore (June, July 2008)
• Visiting Faculty Fellow, Applied Materials, Santa Clara, CA, USA (June - December, 2006)
• Associate Professor, Department of Electrical Engineering, IIT Bombay (March 2005 - February 2009)
• Assistant Professor, Department of Electrical Engineering, IIT Bombay (January 2002 - February 2005)
• PMTS, Bell Laboratories, Murray Hill, NJ, USA (April 2000 - December 2001)

• University gold medal, Jadavpur University, Calcutta (1995)
• PhD fellowship, Siemens AG, Germany (1997 - 1999)
• Innovation Potential of Students Projects Award 2000 - Doctoral Level, Indian National Academy of Engineering (INAE) (2001)
• Young Engineer Award,Indian National Academy of Engineering (INAE) (2004)

• Invited to speak at International Electron Devices Meeting (IEDM), San Francisco, USA, December 2004.
• Invited to speak at Insulating Films on Semiconductors (INFOS) Conference, IMEC, Lueven, Belgium, June 2005.
• Invited to speak at Solid State Devices & Materials (SSDM) Conference, Kobe, Japan, September 2005.
• Tutorial speaker, International Reliability Physics Symposium (IRPS), San Jose, CA, USA, March 2006.
• Tutorial speaker, International Reliability Physics Symposium (IRPS), Phoenix, AZ, USA, April, 2007.
• Invited to speak at International Conference on Solid-State and Integrated-Circuit Technology (ICSICT), Beijing, China, October 2008
• Invited as Tutorial speaker, International Reliability Physics Symposium (IRPS), Montreal, Canada, April, 2009.
• Invited to speak at International Symposium on Silicon Nitride, Silicon Dioxide, and Alternate Emerging Dielectrics (to be held on occasion of 215th Meeting of The Electrochemical Society), San Francisco, CA, USA, May 2009.

• Subcommittee member, International Reliability Physics Symposium 2005, 2008, 2009.
• Technical program chair, 14th International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA), Bangalore, India 2007
• Co-chair, transistor reliability committee, International Reliability Physics Symposium, Phoenix, AZ, USA, April 2007

• Graduate Faculty, School of Electrical Engineering and Computer Science, Purdue University, W. Lafayette, IN, USA (2007 - 2011)

• SONOS Flash EEPROMs (Hitachi, Japan)
• Reliability of ultrathin gate dielectrics (Renesas, Japan)
• Nanocrystal flash (Applied Materials, USA)
• NBTI in ultrathin oxynitrides (Applied Materials, USA; jointly with Purdue University, USA)
• Optimization of Charge Trap Flash for NAND applications (Applied Materials, USA)
• Split gate Flash EEPROM performance, scaling & reliability (TSMC, Taiwan, ROC)
• High-k/MG for memory and logic applications (SRC-GRC, USA)

• ESSDERC 2002, Florence, Italy (September 2002)
• IEDM 2002, San Francisco, CA, USA (December 2002)
• VLSI Design 2003, New Delhi, India (January 2003)
• IEDM 2003, Washington, DC, USA (December 2003)
• IEDM 2004, San Francisco, CA, USA (December 2004, Invited)
• INFOS 2005, IMEC, Leuven, Belgium (June 2005, Invited)
• SSDM 2005, Kobe, Japan (September 2005, Invited)
• IEDM 2005, Washington, DC, USA (December 2005)
• IRPS 2006, San Jose, CA, USA (March 2006, Tutorial)
• IRPS 2007, Phoenix, AZ, USA (April 2007, Tutorial)
• IEDM 2007, Washibgton DC, USA (December 2007)

• Pawan K Singh (Metal Nanocrystal Flash, ongoing)
• Shweta Deora (Reliability of high-k/MG, ongoing)
• Sandhya C (Charge Trap Flash, ongoing)
• Arnab Datta (2Bit SONOS Flash EEPROMs, ongoing)
• Vrajesh Mehta (NBTI in SiON p-MOSFETs, ongoing)
• Gautam Kapila (1/f noise in SiON & high-k FETs, ongoing)
• P Bharath Kumar (SONOS Flash EEPROMs, Completed, March 2007)
• Deleep Nair (CHISEL Flash EEPROMs, Completed, Feb 2005)

• Leela Madhav (NBTI, completed - 2006)
• Sunny Gedam (SONOS Flash, completed - 2006)
• Gaurav Gupta (NBTI, completed - 2006)
• Ch. Sridhar (SONOS modeling, completed - 2006)
• Abhijeet Paul (SONOS modeling, completed - 2006)
• Pawan K Singh (Nanocrystal Flash, completed - 2006)
• Siddharth Sharma (NBTI, completed - 2005)
• Dipankar Saha (NBTI, completed - 2005)
• K. Sridhar (SONOS Flash, completed - 2005)
• Pradeep R. Nair (SONOS Flash, completed - 2004)
• Tapas R. Dalei (NBTI, completed - 2004)
• Anupama Garg (SONOS Flash, completed - 2004)
• P. Bharath Kimar (NBTI, completed-2003)
• Pankaj Pandekar (Ultrathin GoX C-V modeling, completed - 2003)
• Dhanoop Varghese (NBTI - completed 2005)
• P. Bappana Naidu (SONOS Flash - completed 2005)
• Nitesh Jain (SONOS modeling - completed 2005)
• Ravinder Sharma (SONOS Flash - completed 2004)

Department of Electrical Engineering
IIT Bombay, Powai
Mumbai 400 076, India
Email : souvik[AT]ee.iitb.ac.in
Phone (Internal(O)) : (0091 22) - 2576 7412
Phone (Internal(R)) : 8412
Office room no: AA301A
Fax: (0091 22) - 25723707

I do not offer summer internships.

1. S. Mahapatra, S. Shukuri and J. Bude, “CHISEL flash EEPROM part-I: performance and scaling”, IEEE Trans. Electron Devices, v.49, p.1296, 2002.
2. S. Mahapatra, S. Shukuri and J. Bude, “CHISEL flash EEPROM part-II: reliability”, IEEE Trans. Electron Devices, v.49, p.1302, 2002.
3. N. R. Mohapatra, D. R. Nair, S. Mahapatra, V. R. Rao, S. Shukuri and J. Bude, “CHISEL programming operation of scaled NOR Flash EEPROMs – Effect of voltage scaling, device scaling and technological parameters”, IEEE Trans. Electron Devices, v.50, p.2104, 2003.
4. D. R. Nair, N. R. Mohapatra, S. Mahapatra, S. Shukuri and J. Bude, “Effect of P/E cycling on drain disturb in Flash EEPROMs under CHE and CHISEL operation”, IEEE Trans. Device and Materials Reliability, v.4, p.32, 2004.
5. D. R. Nair, S. Mahapatra, S. Shukuri and J. Bude, “Drain disturb during CHISEL programming of NOR Flash EEPROMs – Physical mechanisms and impact of technological parameters”, IEEE Trans. Electron Devices, v.51, p.701, 2004.
6. D. R. Nair, S. Mahapatra and S. Shukuri, “Cycling endurance of NOR Flash EEPROM cells under CHISEL programming operation - Impact of technological parameters and scaling”, IEEE Trans. Electron Devices, v.51, p.1672, 2004.
7. D. R. Nair, S. Mahapatra, S. Shukuri and J. Bude, “Explanation of P/E Cycling Impact on Drain Disturb in Flash EEPROMs under CHE and CHISEL Programming Operation”, IEEE Trans. Electron Devices, v.52, p.534, 2005.
8. P. Bharath, D. Nair and S. Mahapatra, “Using Soft Secondary Electron Programming to reduce Drain Disturb in Floating Gate NOR Flash EEPROMs”, IEEE Trans. Device and Materials Reliability, v.6, p.81, 2006.
9. P. Bharath Kumar, P. R. Nair, R. Sharma, S. Kamohara and S. Mahapatra, “Lateral profiling of trapped charge in SONOS Flash EEPROMs programmed using channel hot electron injection”, IEEE Trans. Electron Devices, v.53, p.698, 2006.
10. P. Bharath Kumar, R. Sharma, P. R. Nair and S. Mahapatra, “Investigation of drain disturb in SONOS Flash EEPROMs”, IEEE Trans. Electron Devices, v.54, p.98, 2007.
11. A. Datta, P. Bharath Kumar and S. Mahapatra, “Dual-bit/Cell SONOS Flash EEPROMs: Impact of Channel Engineering on Programming Speed and Bit Coupling Effect”, IEEE Electron Dev. Lett., p.446, v.28, 2007

1. S. Mahapatra, S. Shukuri and J. Bude, “Performance and reliability of high-density flash EEPROMs under CHISEL programming operation”, Proceedings, 32nd European Solid-State Device Research Conference (ESSDERC), Florence, Italy, p., 2002.
2. S. Mahapatra, S. Shukuri and J. Bude, “Substrate bias effect on cycling induced performance degradation of scaled flash EEPROMs”, Proceedings, 16th IEEE VLSI Design Conference, New Delhi, India, p.223, 2003.
3. N. R. Mohapatra, S. Mahapatra, V. R. Rao, S. Shukuri and J. Bude, “Effect of programming biases on the reliability of CHE and CHISEL flash EEPROMs”, Proceedings, Int. Reliability Phys. Symp (IRPS), Dallas, USA, p.518, 2003.
4. D. R. Nair, N. R. Mohapatra, S. Mahapatra, S. Shukuri and J. Bude, “The effect of CHE and CHISEL programming operation on drain disturb in flash EEPROMs”, Proceedings, 10th International Symposium on the Physical and Failure Analysis of Integrated Circuits, Singapore, p.164, 2003.
5. N. R. Mohapatra, D. R. Nair, S. Mahapatra, V. R. Rao and S. Shukuri, “The Impact of Channel Engineering on the Performance Reliability and Scaling of CHISEL NOR Flash EEPROMs”, Proceedings, 33rd European Solid State Device Research Conference (ESSDERC), Lisbon, Portugal, p.541, 2003.
6. D. R. Nair, N. R. Mohapatra, S. Mahapatra and S. Shukuri, “The Impact of Technology Parameters and Scaling on the Programming Performance and Drain Disturb in CHISEL Flash EEPROMs”, Proceedings, International Conference on Solid State Devices and Materials (SSDM), Tokyo, Japan, p.644, 2003.
7. D. R. Nair, S. Mahapatra, S. Shukuri and J. Bude, “Multi-Level Programming of NOR Flash EEPROMs by CHISEL Mechanism”, Proceedings, Int. Reliability Phys. Symp (IRPS), Phoenix, USA, p.635, 2004.
8. P. R. Nair, P. Bharath Kumar, R. Sharma, S. Kamohara and S. Mahapatra, “A Comprehensive Trapped Charge Profiling Technique for SONOS Flash EEPROMs”, Proceedings, International Electron Devices Meeting (IEDM), San Francisco, CA, USA, p.403, 2004.
9. P. Bharath Kumar, Ravinder Sharma, Pradeep R. Nair, Deleep R. Nair, S. Kamohara, S. Mahapatra, and J. Vasi, “Mechanism of drain disturb in SONOS Flash EEPROMs”, Int. Reliability Phys. Symp (IRPS), San Jose, USA, p.186, 2005.
10. P. Bharath Kumar, D. R. Nair, and S. Mahapatra, “Soft Secondary Electron Programming for Floating Gate NOR Flash EEPROMs”, International Symposium on the Physical and Failure Analysis of Integrated Circuits, Singapore, p.146, 2005.
11. K. Sridhar, P. Bharath Kumar, S. Mahapatra, E. Murakami , and S. Kamohara, “Controlling Injected Electron and Hole Profiles for Better Reliability of Split Gate SONOS “, International Symposium on the Physical and Failure Analysis of Integrated Circuits, Singapore, p.190, 2005.
12. P. Bharath Kumar, Ravinder Sharma, E. Murakami , S. Kamohara, and S. Mahapatra, “Effect of Compensation Implant in SONOS Flash EEPROMs”, International Conference on Solid State Devices and Materials (SSDM), Tokyo, Japan, p.644, 2005.
13. P. Bharath Kumar, E. Murakami, S. Kamohara, S. Mahapatra, “Endurance and Retention Characteristics of SONOS EEPROMs operated using BTBT Induced Hot Hole Erase”, Int. Reliability Phys. Symp (IRPS), San Jose, USA, p.?, 2006.
14. A. Paul, Ch. Sridhar, S. Gedam and S. Mahapatra, “Comprehensive simulation of program, erase and retention in charge trapping flash memories”, International Electron Devices Meeting (IEDM), San Francisco, CA, USA, p.393, Dec 2006.
15. A. Nainani, S. Palit, P. K. Singh, U. Ganguly, N. Krishna, J. Vasi and S. Mahapatra, “Development of A 3D Simulator for Metal Nanocrystal (NC) Flash Memories under NAND Operation”, presented, International Electron Devices Meeting (IEDM), Washington DC, USA, Dec 2007.
16. Sandhya C., U. Ganguly, K.K. Singh, P.K. Singh, C. Olsen, S. Seutter, G. Conti, K. Ahmed, N. Krishna, J. Vasi, and S. Mahapatra; “Nitride engineering and the effect of interfaces on Charge Trap Flash performance”, accepted, Int. Reliability Phys. Symp (IRPS), Phoenix, AZ (2008)

1. S. Mahapatra, P. Bharath Kumar and M. A. Alam, “Investigation and Modeling of Interface and Bulk Trap Generation During Negative Bias Temperature Instability of p-MOSFETs”, IEEE Trans. Electron Devices, v.51, p.1371, 2004.
2. M. A. Alam and S. Mahapatra, “A Comprehensive Model of PMOS NBTI Degradation”, Microelectronics Reliability, special issue on NBTI, v.45, p.71, 2005 (Invited paper)
3. S. Mahapatra, M. A. Alam, P. Bharath Kumar, T. R. Dalei, D. Varghese and D. Saha, “Negative bias temperature instability in CMOS devices”, Microelectronics Engineering, special issue on INFOS, v.80, p.114, 2005 (Invited paper).
4. D. Varghese, S. Mahapatra and M. A. Alam, “Hole energy dependent interface trap generation in MOSFET Si/SiO2 interface”, IEEE Electron Devices Lett., v.26, p.572, Aug. 2005.
5. D. Saha, D. Varghese and S. Mahapatra, “On the Generation and Recovery of Hot Carrier Induced Interface Traps: A critical examination of the 2D Reaction Diffusion model”, IEEE Electron Devices Lett., v.27, p.188, 2006.
6. D. Saha, D. Varghese and S. Mahapatra, “The role of Anode Hole Injection and Valence Band Hole Tunneling on interface trap generation during hot carrier injection stress”, IEEE Electron Devices Lett., p.585, 2006.
7. S. Mahapatra, D. Saha, D. Varghese and P. Bharath Kumar, “On the generation and recovery of interface traps in MOSFETs subjected to NBTI, FN and HCI stress”, IEEE Trans. Electron Devices, p.1583, 2006.
8. M. A. Alam, H. Kufluoglu, D. Varghese and S. Mahapatra, “A Comprehensive Model of PMOS NBTI Degradation: Recent progress”, Microelectronics Reliability, in press.
9. D. Varghese, G. Gupta, L. Madhav, D. Saha, K. Ahmed, F. Nouri and S. Mahapatra, “Physical Mechanism and Gate Insulator Material Dependence of Generation and Recovery of Negative Bias Temperature Instability in p-MOSFETs”, IEEE Trans. Electron Devices, p.1672, v.54, July 2007.
10. A. E. Islam, H. Kufluoglu, D. Varghese, S. Mahapatra and M. A. Alam, “Recent issues in negative bias temperature instability: Initial degradation, field dependence of interface trap generation, hole trapping effects and relaxation”, IEEE Trans. Electron Devices, p.2143, v.54, September, 2007.
11. S. Mahapatra and M. A. Alam, “Defect generation in p-MOSFETs under negative bias stress: An experimental perspective”, IEEE Trans. Device & Materials Reliability, p.35, v.8, March 2008
12. A. E. Islam, G. Gupta, K. Z. Ahmed, S. Mahapatra and M. A. Alam, “Optimization of gate leakage and NBTI for Plasma Nitrided gate oxides by numerical and analytical methods”, accepted, IEEE Trans. Electron Devices, to appear May 2008.

1. S. Mahapatra and M. A. Alam, “A predictive reliability model for PMOS bias temperature degradation”, Tech. Digest, International Electron Devices Meeting (IEDM), San Francisco, CA, USA, p.505, 2002.
2. S. Mahapatra, P. Bharath Kumar and M. A. Alam, “A new observation of enhanced bias temperature instability in thin gate oxide p-MOSFET”, Tech. Digest, International Electron Devices Meeting (IEDM), Washington, DC, USA, p.337, 2003.
3. S. Mahapatra, M. A. Alam, P. Bharath Kumar, T. R. Dalei and D. Saha, “Mechanism of Negative Bias Temperature Instability in CMOS Devices: Degradation, Recovery and Impact of Nitrogen”, Invited paper, International Electron Devices Meeting (IEDM), San Francisco, CA, USA, p.105, 2004.
4. P. Bharath Kumar, T. R. Dalei, D. Varghese, D. Saha, S. Mahapatra and M. A. Alam, “Impact of Substrate Bias on p-MOSFET Negative Bias Temperature Instability”, accepted, Int. Reliability Phys. Symp (IRPS), San Jose, USA, p.700, 2005.
5. D. Varghese, D. Saha, S. Mahapatra, K. Ahmed, F. Nouri and M. Alam, “On the dispersive versus arrhenius temperature activation of NBTI time evolution in plasma nitrided gate oxides: Measurements, theory and implications”, International Electron Devices Meeting (IEDM), Washington, DC, USA, p.684, Dec 2005.
6. A. E. Islam, G. Gupta, S. Mahapatra, A. T. Krishnan, K. Ahmed, F. Nouri, A. Oates and M. A. Alam, “Gate leakage vs. NBTI in plasma nitrided oxides: Characterization, physical principles and optimization”, Accepted, International Electron Devices Meeting (IEDM), San Francisco, CA, USA, p.403, 2006.
7. S. Mahapatra, K. Ahmed, D. Varghese, A. E. Islam, G. Gupta, L. Madhav, D. Saha and M. A. Alam, “On the Physical Mechanism of NBTI in Silicon Oxynitride p-MOSFETs: Can Differences in Insulator Processing Conditions Resolve the Interface Trap Generation versus Hole Trapping Controversy?”, Int. Reliability Physics Symp (IRPS), Phoenix, AZ, USA, p.1, April 2007.
8. A.E. Islam, E. N. Kumar, H. Das, S. Purawat, V. Maheta, H. Aono, E. Murakami, S. Mahapatra, and M.A. Alam, “Theory and Practice of Ultra-fast Measurements for NBTI Degradation: Challenges and Opportunities”, presented, International Electron Devices Meeting (IEDM), Washington DC, USA, Dec 2007.
9. E. N. Kumar, V. D. Maheta, S. Purawat, A. E. Islam, C. Olsen, K. Ahmed, M. A. Alam and S. Mahapatra, “Material Dependence of NBTI Physical Mechanism in Silicon Oxynitride (SiON) p-MOSFETs: A Comprehensive Study by Ultra-Fast On-The-Fly (UF-OTF) IDLIN Technique”, presented, International Electron Devices Meeting (IEDM), Washington DC, USA, Dec 2007.
10. A. E. Islam, V. D. Maheta, H. Das, S. Mahapatra and M. A. Alam, “Mobility degradation due to interface traps in plasma oxynitride PMOS devices”, accepted, Int. Reliability Physics Symp (IRPS), Phoenix, AZ, USA (2008).

1. K. G. Anil, S. Mahapatra, V. R. Rao and I. Eisele, “Comparison of sub-bandgap impact ionization in deep-submicron conventional and lateral asymmetric channel n-MOSFETs”, Jpn. J. Appl. Phys., v.40, p-I, no.4B, p.2621, April 2001.
2. K. G. Anil, S. Mahapatra and I. Eisele, “Observation of double peak in the substrate current versus gate voltage characteristics in n-channel MOSFETs”, Appl. Phys. Lett., v.78, no.15, p.2238, April 2001.
3. K. G. Anil, S. Mahapatra and I. Eisele, “Experimental verification of the nature of the high energy tail in the electron energy distribution in n-channel MOSFETs”, IEEE Electron Devices Lett., v.22, p.478, Oct. 2001.
4. K. G. Anil, S. Mahapatra and I. Eisele, “Electron-electron interaction signature peak in the substrate current vs gate voltage characteristics of n-channel silicon MOSFETs”, IEEE Trans. Electron Devices v.49, p.1283, 2002.
5. K. G. Anil, S. Mahapatra and I. Eisele, “A detailed experimental investigation of impact ionization in n-channel metal-oxide-semiconductor field-effect-transistors at very low drain voltages”, Solid State Electron, v.47, p.995, 2003.

1. Anil K. G., S. Mahapatra and I. Eisele, “Role of inversion layer quantization on sub-bandgap impact ionization in deep-sub-micron n-channel MOSFETs”, Tech. Digest, International Electron Devices Meeting (IEDM), San Francisco, CA, USA, p.675, 2000.

1. S. Mahapatra, V. R. Rao, C. D. Parikh, J. Vasi, B. Cheng and J. C. S. Woo, “A study of 100 nm channel length asymmetric channel MOSFET by using charge pumping”, Microelectronics Engineering, v.48, p.193, Sept 1999.
2. S. Mahapatra, C. D. Parikh, V. R. Rao, C. R. Viswanathan and J. Vasi, “A comprehensive study of hot-carrier induced interface and oxide trap distributions in MOSFETs using a novel charge pumping technique”, IEEE Trans. Electron Devices, v.47, p.171, Jan 2000.
3. S. Mahapatra, C. D. Parikh, V. R. Rao, C. R. Viswanathan and J. Vasi, “Device scaling effects on hot-carrier induced interface and oxide trapped charge distributions in MOSFETs”, IEEE Trans. Electron Devices, v.47, p.789, April 2000.
4. S. Mahapatra, V. R. Rao, B. Cheng, M. Khare, C. D. Parikh, J. C. S. Woo and J. Vasi, “Performance and Hot-Carrier Reliability of 100 nm Channel Length Jet Vapor Deposited Si3N4 MNSFETs”, IEEE Trans. Electron Devices, v.48, p.679, April 2001.
5. S. Mahapatra, V. R. Rao, C. D. Parikh, J. Vasi, B. Cheng and J. C. S. Woo, “A study of hot-carrier induced interface trap profiles in lateral asymmetric channel MOSFETs using a novel charge pumping technique”, Solid State Electron, v.45, p.1717, 2001.

1. S. Mahapatra, V. R. Rao, K. N. ManjulaRani, C. D. Parikh, J. Vasi, B. Cheng, M. Khare and J. C. S. Woo, “100 nm channel length MNSFETs using a Jet Vapor Deposited ultra-thin silicon nitride gate dielectric”, Tech. Digest, International Symposium on VLSI Technology, Kyoto, Japan, p.79, 1999.
2. S. Mahapatra, V. R. Rao, C. D. Parikh, J. Vasi, B. Cheng, M. Khare and J. C. S. Woo, “Hot-carrier induced interface degradation in Jet Vapor Deposited SiN MNSFETs as studied by a novel charge pumping technique”, Proceedings, 29th European Solid State Device Research Conference (ESSDERC), Leuven, Belgium, p.592, 1999.
3. S. Mahapatra, K. N. ManjulaRani, V. R. Rao and J. Vasi, ‘ULSI MOS transistors with Jet Vapor Deposited (JVD) silicon nitride for the gate insulator”, Proceedings, 10th International Workshop on Physics of Semiconductor Devices (IWPSD), New Delhi, India, p., 1999.
4. S. Mahapatra, V. R. Rao, C. D. Parikh, J. Vasi, B. Cheng and J. C. S. Woo, “Hot-carrier induced interface trap distributions in conventional and asymmetric channel MOSFETs as determined by a novel charge pumping technique”, 29th IEEE Semiconductor Interface Specialists Conf. (SISC), South Carolina, USA, 1999.
5. S. Mahapatra, V. R. Rao, J. Vasi, B. Cheng, and J.C.S. Woo, “Reliability Studies on Sub 100 nm SOI-MNSFETs”, International Integrated Reliability Workshop (IRW), Stanford, CA, USA, 2000.
6. V. R. Rao, S. Mahapatra, J. Vasi, K. G. Anil, C. Fink, W. Hansch and I. Eisele, “Hot-carrier performance of 60 nm channel length delta-doped vertical MOSFETs with high-pressure grown oxide as a gate dielectric”, 30th IEEE Semiconductor Interface Specialists Conference (SISC), San Diego, California, USA, 2000.
7. Anil K. G., S. Mahapatra, I. Eisele, V. R. Rao and J. Vasi, “Drain bias dependence of gate oxide reliability in conventional and asymmetrical channel MOSFETs in the low voltage regime”, Proceedings, 30th European Solid State Device Research Conference (ESSDERC), Cork, Ireland, p.124, 2000.
8. N. R. Mohapatra, S. Mahapatra, V. R. Rao, “”Study of Degradation in Channel Initiated Secondary Electron Injection Regime”, Proceedings, 31st European Solid-State Device Research Conference (ESSDERC), 11 - 13 September 2001, Nuremberg, Germany, p. 2001.
9. N. R. Mohapatra, S. Mahapatra and V. R. Rao, “A Comparative Study of Degradation for n-MOSFET’s in CHE and CHISEL Injection Regime”, Proceedings, 11th International Workshop on The Physics of Semiconductor Devices, New Delhi, India, p., 2001
10. N. R. Mohapatra, S. Mahapatra and V. R. Rao, “The study of damage generation in n-channel MOS transistors operating in the substrate enhanced gate current regime”, Proceedings, 9th International Symposium on the Physical and Failure Analysis of Integrated Circuits, Singapore, p. 27, 2002.
11. N. R. Mohapatra, S. Mahapatra and V. R. Rao, “Device Scaling Effects on Substrate Enhanced Degradation in MOS Transistors”, 2002 MRS Spring Meeting, San Francisco, CA, USA, April 1-5, 2002.

1. S. Mahapatra, C. D. Parikh and J. Vasi, “A new ‘multifrequency’ charge pumping technique to profile hot-carrier induced interface-state density in n-MOSFETs”, IEEE Trans. Electron Devices, v.46, p.960, May 1999.
2. S. Mahapatra, C. D. Parikh, J. Vasi, V. R. Rao and C. R. Viswanathan, “A direct charge pumping technique for spatial profiling of hot-carrier induced interface and oxide traps in MOSFETs”, Solid State Electron, v.43, p.913, June 1999.

1. S. Mahapatra, C. D. Parikh and J. Vasi, “A new technique to profile hot-carrier induced interface-state generation in n-MOSFETs using charge pumping”, Proceedings, 9th International Workshop on Physics of Semiconductor Devices (IWPSD), New Delhi, India, p. 1030, 1997.
2. S. Mahapatra, C. D. Parikh and J. Vasi, “A reliable approach to determine hot-carrier induced interface state distribution in n-MOSFET using charge pumping”, Proceedings, International Conference on Computers and Devices for Communication (CODEC), Calcutta, India, p. 373, 1998.
3. A. Kumar, S. Mahapatra, R. Lal and V. R. Rao, “Multi-frequency transconductance technique for interface characterization of deep sub-micron SOI-MOSFETs”, 11th Workshop on Dielectrics in Microelectronics (WoDiM), Munich, Germany, 2000.
4. G. Shrivastav, S. Mahapatra, V. R. Rao, J. Vasi, K. G. Anil, C. Fink, W. Hansch and I. Eisele, “Performance Optimization of 60 nm Channel Length Vertical MOSFETs Using Channel Engineering”, Proceedings, 14th IEEE VLSI Design Conference, Bangalore, India, p.475, 2001.