Udayan Ganguly

Udayan's Google Scholar Citation Index
h-index: 11
i10-index: 13

My overall interest is in experimental device physics with modeling/design

• Resistance Random Access Memory RRAM- materials, devices - fabrication, characterization and modeling (with S. Lodha)
• Advanced Logic Device Engineering - FinFET devices - design, fabrication, characterization and modeling (with S. Lodha, S. Ganguly, A. Laha, and S. Mahapatra)

• Ph.D. Materials Science and Engineering Cornell University, 2006
• M.S., Materials Science and Engineering Cornell University, 2005
• B. Tech., Metallurgical Engineering Indian Institute of Technology Madras (IITM), 2000

• Employee of the Quarter, Front End Products, Applied Materials 2010
• Outstanding Paper Award at IEEE Intl. Workshop on Electron Devices and Semiconductor Technology (IEDST) 2009
• MRS Trophy Award for best manuscript in Symposium D (MRS Fall 2004, Boston)

• 2010 Fall EE236 Electronic Devices Lab
• 2011 Spring EE214 Digital Circuits Lab
• 2011 Fall EE236 Electronic Devices Lab
• 2012 Spring EE620 Physics of Transistors
• 2012 Fall EE101 Introduction to Electrical Engineering
• 2013 Spring EE620 Physics of Transistors

1. P. Paramhans, R. K. Mishra, V. P. Kishore, P. Ray, A. Nainani, Y.-C. Huang, M. C. Abraham, U. Ganguly and S. Lodha, “Fermi-level unpinning and low resistivity in contacts to n-type Ge with a thin ZnO interfacial layer”, to appear in Applied Physics Letters, 2012
2. V. S. S. Srinivasan, S. Chopra, P. Karkare, P. Bafna, S. Lashkare, P. Kumbhare, Y. Kim, S. Srinivasan, S. Kuppurao, S. Lodha, U. Ganguly, “Punch-through Diode based Bipolar RRAM Selector by Si Epitaxy”, IEEE Electron Devices Letters, v. 33 , pp. 1396, 2012.
3. V. P. Kishore, P. Paramahans, S. Sadana, U. Ganguly, and S. Lodha, “Nanocrystal-based Ohmic contacts on n and p-type germanium”, Appl. Phys. Lett. 100, 142107, 2012
4. U. Ganguly, T. Guarini, D. Wellekens, L. Date, Y. Cho, A. Rothschild, J. Swenberg, “Impact of Top-Surface Tunnel Oxide Nitridation on Flash Memory Performance and Reliability,” IEEE Electron Device Letters , v.31, pp.123-125, 2010.
5. C. Sandhya, A. B. Oak, N. Chattar, U. Ganguly, C. Olsen, S. M. Seutter, L. Date, R. Hung, J. Vasi, and S. Mahapatra, ‘Study of Endurance Induced Degradation Mechanism in SANOS Memories under NAND (FN/FN) Operation’, under review, IEEE Transactions on Electron Devices.
6. C. Sandhya, A. B. Oak, A.S. Joshi, N. Chattar, U. Ganguly, C. Olsen, S. M. Seutter, L. Date, R. Hung, J. Vasi, and S. Mahapatra, ‘Impact of SiN Composition Variation on SANOS Memory Performance and Reliability under NAND (FN/FN) Operation’, IEEE Transactions on Electron Devices. v. 56, pp. 3123-3132, 2009.
7. C. Sandhya, U. Ganguly, N. Chattar, C. Olsen, S. M. Seutter, L. Date, R. Hung, J. Vasi, and S. Mahapatra, “Effect of SiN on Performance and Reliability of Charge Trap Flash (CTF) Under Fowler Nordheim Tunneling Program/Erase Operation” IEEE Electron Device Letters v.30, No.2 pp. 171-173, 2009.
8. U. Ganguly, T.-H. Hou, E. C. Kan, ‘Enhanced Electrostatics for Low-Voltage Operations in Nanocrystal based Nanotube/Nanowire Memories’, IEEE Trans. Nanotechnology, 6, 22, 2007.
9. T.-H. Hou, U. Ganguly, and E. C. Kan, ‘Fermi-Level Pinning in Nanocrystal Memories’, IEEE Electron Device Letters, 28, 103, 2007.
10. T.-H. Hou, U. Ganguly, and E. C. Kan, ‘Programmable Molecular Orbital States of C60 from Integrated Circuits,’ Applied Physics Letters, 89, 253113, 2006.
11. U. Ganguly, V. Narayanan, C. Lee, T.-H. Hou, E. C. Kan, ‘Three dimensional analytical modeling of nanocrystal memory electrostatics’, Journal of Applied Physics, 99, 114516 2006.
12. T. -H. Hou, C. Lee, V. Narayanan, U. Ganguly, E. C. Kan, ‘Design Optimization of Metal Nanocrystal Memory—Part II: Gate-Stack Engineering’, IEEE Transactions on Electron Devices, 53, 3103, 2006.
13. T. -H. Hou, C. Lee, V. Narayanan, U. Ganguly, E. C. Kan, ‘Design Optimization of Metal Nanocrystal Memory—Part II: Gate-Stack Engineering’, IEEE Transactions on Electron Devices, 53, 3095, 2006.
14. U. Ganguly, E.C. Kan, Y. Zhang, ‘Carbon nanotube FET memory with charge storage in metal nanocrystal’, Applied Physics Letters, 87, 043108 (2005).
15. C. Lee, U. Ganguly, V. Narayanan, T.-H Hou, and E. C. Kan, ‘Asymmetric Electric Field Enhancement in Nanocrystal Memories’, IEEE Electron Device Letters, 26, 879, 2005.
16. J. Guo, E. C. Kan, U. Ganguly, Y. Zhang, ‘High Sensitivity and Non-Linearity of Carbon-Nanotube-Based Charge Sensors’, Journal of Applied Physics, 99, 084301 2006.
17. U. Ganguly, J. P. Krusius, “Fabrication of Ultra-Planar Aluminum Mirror Array by Novel Encapsulation CMP for Micro-optics and MEMS applications” Journal of Electrochemical Society, 151, H232, 2004.
18. U. Ganguly, J. P. Krusius, “Novel compensation CMP for low dishing and high global planarity for ultra-planar die applications in micro-optics and MEMS”, Thin Solid Films, 460,306, 2004.

1. S. Mittal, S. Gupta, A. Nainani, M. Abhraham, K. Schuegraf, S. Lodha, and U. Ganguly, " Epi Defined (ED) FinFET: An alternate device architecture for high mobility Ge channel integration in PMOSFET” 5th IEEE International Nanoelectronics Conference, IEEE INEC 2013.
2. R. Mandapati, A. Borkar, S. Srinivasan, P. Bafna, P. Karkare, S. Lodha, and U.Ganguly, “On Pairing Bipolar RRAM memory element with novel punchthrough diode based selector: Compact modeling to array performance” 5th IEEE International Nanoelectronics Conference, IEEE INEC 2013.
3. N. Panwar, G. Rao, N. R. C. Raju, R. Nori, P. Kumbhare, S. Deshmukh, V. S. S. Srinivasan , N. Venkataramani, U. Ganguly, “Thermal Budget Reduction for Back-end Compatibility and Control of Resistance Switching Mechanism (Unipolar to Bipolar) in Pr1-xCaxMnO3 (PCMO) RRAM” MRS Fall, AA9.27, Boston, 2012
4. R. Nori, N. R. C. Raju, N. Thomas, N. Panwar, P. Kumbhare, G. Rao, V. S. S. Srinivasan, N. Venkataramani, U. Ganguly, “Conducting Oxide Electrode to Mitigate Mechanical Instability (Bubble Formation) during Operation of La1-xSrxMnO3 (LSMO) Based RRAM” MRS Fall A12.40, Boston, 2012.
5. S. Deshmukh, R. Mandapati, S. Lashkare, A. Borkar, V.S.S. Srivinasan, S. Lodha, U. Ganguly, “Comparison of novel punch-through diode (NPN) selector with MIM selector for Bipolar RRAM” Non Volatile Memory Technology Symposium, Singapore, 2012
6. S. Chopra, P. Bafna, P. Karkare, S. Srinivasan, S. Lashkare, P. Kumbhare, Y. Kim, S. Srinivasan, S. Kuppurao, S. Lodha, and U. Ganguly, “A Two Terminal Vertical Selector Device for Bipolar RRAM”, Pacific Rim Meeting on Electrochemical and Solid State Science (PRiME), Honolulu, Hawaii, USA, October 7-12 2012 (accepted).
7. P. Bafna, P. Karkare, S Srinivasan, S. Chopra, S. Lashkare, Y. Kim, S. Srinivasan, S. Kuppurao, S. Lodha, U. Ganguly, “Epitaxial Si Punch-Through based Selector for Bipolar RRAM”, DRC 2012
8. S. Mittal, S. Gupta, A. Nainani, M.C. Abraham, K. Schuegraf, S. Lodha, U. Ganguly, “Epitaxialy defined (ED) FinFET: to reduce VT variability and enable multiple VT”, Device Research Conference 2012
9. P. Paramahans, P. Ray, S. Mane, P. Nyaupane, U. Ganguly, S. Lodha, “Ohmic contacts to n-type Germanium using a thin ZnO interfacial layer” in MRS Spring Meeting, San Francisco 2012.
10. V. Pavan Kishore, P. Paramahans, S. Sadana, U. Ganguly, S. Lodha, “Contact Resistance Reduction on Germanium through Metal Work Function Engineering” in MRS Spring Meeting, San Francisco 2012
11. P. Paramahans, S. Gupta, R. K. Mishra, N. Agarwal, A. Nainani, Y. Huang, M.C. Abraham, S. Kapadia, U. Ganguly, S. Lodha, “ZnO: an attractive option for n-type metal-interfacial layer-semiconductor (Si, Ge, SiC) contacts”, VLSI Symp 2012
12. V. P. Kishore, P. Paramahans, S. Sadana, U. Ganguly, S. Lodha, “Novel Nanocrystal-based contacts to n and p-type Germanium”, Physics and Chemistry of Surfaces and Interfaces (PCSI) 2012
13. U. Ganguly, Y. Yokota, J. Tang, S. Sun, M. Rogers, M. Jin , K. Thadani, H. Hamana, G. Leung, B. Chandrasekaran, S. Thirupapuliyur, C. Olsen, V. Nguyen, S. Srinivasan, “Scalability Enhancement of FG NAND by FG Shape Modification” International Memory Workshop, Seoul 2010.
14. C. Sandhya, U. Ganguly, B. Apoorva, C. Olsen, S. Seutter, L. Date, R. Hung, J. Vasi and S. Mahapatra, ‘Influence of SiN composition on Program and Erase Characteristics of SANOS-type Flash Memories’, in IEEE Intl. Workshop on Electron Devices and Semiconductor Technology (IEDST) 2009. Received the Outstanding Paper Award*
15. Sandhya C., U. Ganguly, K.K. Singh, P.K. Singh, R. Hung, C. Olsen, S. M. Seutter, G. Conti, K. Ahmed,N. Krishna, J. Vasi, and S. Mahapatra, ‘The Effect of Band Gap Engineering of the Nitride Storage Node on Performance and Reliability of Charge Trap Flash’, International Physics of Failure Analysis (IPFA), 2008
16. Sandhya C., U. Ganguly, K.K. Singh, P.K. Singh, R. Hung, C. Olsen, S. M. Seutter, G. Conti, K. Ahmed,N. Krishna, J. Vasi, and S. Mahapatra, ‘Nitride engineering and the effect of interfaces on Charge Trap Flash performance’, International Reliability Physics Symposium (IRPS), 2008
17. A. Nainani, S. Palit, P. K. Singh, U. Ganguly, N. Krishna, J. Vasi and S. Mahapatra, ‘Development of A 3D Simulator for Metal Nanocrystal (NC) Flash Memories under NAND Operation’, International Electron Devices Meeting (IEDM) 2007.
18. U. Ganguly, T.-H. Hou and E. C. Kan, ‘Process Integration of Composite High-k Tunneling Dielectric for Nanocrystal Based Carbon Nanotube Memory’, (MRS) Material Research Symposium, Boston, MA, Dec. 2006.
19. U. Ganguly, T.-H. Hou and E. C. Kan, ‘Quantum Transport and Trap Effects in Tunneling Rate Measurements of Metal Nanocrystal Based Carbon Nanotube Memory’, (MRS) Material Research Symposium, Boston, MA, Dec. 2005.
20. U. Ganguly, C. Lee and E. C. Kan, ‘Retention characteristics for nonvolatile memory based on metal nanocrystals and carbon nanotube FET with CVD SiO2 and ALD HfO2 tunneling dielectrics’, (MRS) Material Research Symposium, Boston, MA, Dec. 2005.
21. U. Ganguly, J. Guo, E. C. Kan and Y. Zhang, ’Carbon nanotubes based non-volatile memory and charge sensors’, Proc. of SPIE Conference, vol. 6003, Oct., 2005. (Invited paper)
22. U. Ganguly, C. Lee and E. C. Kan , ‘Experimental Observation of Non-Volatile Charge Injection and Molecular Redox in Fullerenes C60 and C70 in an EEPROM Type Device’, (MRS) Material Research Symposium, Boston, MA, Dec. 2004. MRS Trophy Award for best paper in Symposium D
23. C. Lee, U. Ganguly and E. C. Kan, ‘Characterization of Number Fluctuations in Gate-last Metal Nanocrystal Nonvolatile Memory Array Beyond 90nm CMOS Technology’, (MRS) Material Research Symposium, Boston, MA, Dec. 2004.
24. U. Ganguly, C. Lee and E. C. Kan, ‘Interface and oxide contamination monitoring in integration of fullerenes and carbon nanotubes with aggressively scaled CMOS gate stacks’, (MRS) Material Research Symposium, Boston, MA, Dec. 2003.

1. S. Mittal, S. Gupta, U. Ganguly, A. Nainani, S. Lodha, S. Ganguly, M. Abraham, E.-X. Ping, “Transistor design for improved performance and variability and method of fabrication”, IITB IDF, PAT/EE/UG-1/12-13
2. U. Ganguly, S. Lodha, P. Bafna, P. Karkare, P. Kumbhare, S. Srinivasan, “Selector device for bipolar RRAM,” Indian Patent Application, 1727/MUM/2011
3. P. Paramhans, S. Lodha, U. Ganguly, A. Nainani, M. Abraham, “Transistor design for improved performance and variability and method of fabrication”, US Patent (applied)
4. J. Swenberg, D. Chu, T. K. Guarini, Y. Cho, U. Ganguly, L. Date, " Enhancing NAND Flash Floating Gate Performance, " Applied Materials Inc, 20100317186
5. U. Ganguly, C Olsen, S M Seutter L Date, “Multi-Layer Charge Trap Silicon Nitride/Oxynitride Layer Engineering with Interface Region Control” Applied Materials Inc, 20110101442
6. U. Ganguly, J. M. Ranish, A. M. Hunter, J. Tang, C. S. Olsen, M. D. Scotney-Castle, V. Nguyen, S. Srinivasan, W. Liu, J. F. Swenberg, S. Sun, “Apparatus and Methods for Cyclical Oxidation and Etching,” Applied Materials Inc., 20110065276
7. U. Ganguly, Y. Yokota, C. S. Olsen, M. D. Scotney-Castle, V. Nguyen, S. Srinivasan, W. Liu, J. F. Swenberg, J. A. Marin, A. Balakrishna, J. Newman, S. C. Hickerson, “Apparatus and Methods for Cyclical Oxidation and Etching,” Applied Materials Inc., 20110061812
8. U. Ganguly, J. M. Ranish, A. M. Hunter, J. Tang, C. S. Olsen, M. D. Scotney-Castle, V. Nguyen, S. Srinivasan, J. F. Swenberg, A. Wang, N. K. Ingle, M. Hemkar, J. A. Marin, “Apparatus and Methods for Cyclical Oxidation and Etching,” Applied Materials Inc., 20110061810
9. C. S. Olsen, S. Sun, T. W. Poon, U. Ganguly, J. Swenberg, “Modification of charge trap silicon nitride with oxygen plasma,” Applied Materials Inc., 20100270609
10. C. S. Olsen, J. Swenberg, U. Ganguly, T. K. Guarini, Y. Cho, “Method of Selective Nitridation,” Applied Materials Inc., 20100248435
11. U. Ganguly, Y. Yokota, J. Tang, S. Thirupapuliyur, C. S. Olsen, S. Sun, T. W. Poon, W. Liu, J. Swenberg, V. U. Nguyen, S. Srinivasan, J. Newman, “Semiconductor devices suitable for narrow pitch applications and methods of fabrication thereof,” Applied Materials Inc., 20100062603
12. Y. Zhang, U. Ganguly, E. C. Kan " Nanotube- and nanocrystal-based non-volatile memory,” Intel Corp, US 7262991

• “Non-volatile memory Engineering- Capabilities and Future Directions at IIT Bombay”, India Research Network Meeting, Organized by Samsung India Software Operations, Bangalore, May 2012.
• “Floating Gate Scaling Roadmap” Applied Materials Technology Forum 2007

• Presented CEN related research activities at NIT Calicut 2012
• Presented CEN related research activities at Science College, Calcutta University, 2011
• Coordinated with Prof S. Lodha for India’s first " Semiconductor Technology and Manufacturing Course” under Continuing Education Program - with Applied Materials Inc 19th-25th Nov 2012
• Moderated a panel discussion on “Catalyzing & Sustaining Semiconductor Manufacturing in India” organized during International Conference on Emerging Electronics (Jointly organized by IIT Bombay & IISc Bangalore)December 15-17, 2012 on behalf of DeitY; Panelists were Dr Ajay Kumar DeitY; Dr Zarabi (Empowered Committee), Dr. PVG Menon (Indian Semiconductor Association), Dr Subu Iyer (Fellow, IBM), Dr Om Nalamasu (CTO, Applied Materials Inc)

Undergraduate

1. Siddharthh Buddhiraju
2. Abhijit Borkar

M. Tech. students

1. Shalini Shrivastava
2. Pankaj Kumbhare
3. Sandip Lashkare
4. Sanchit Deshmukh
5. Ajit Kumar (shared with N Venkatramani MEMS)

Ph. D. students

1. Sushant Mittal
2. Neeraj Panwar
3. Rajashree Nori (shared with V Ramgopal Rao)
4. Raju Mandapati
5. Prashanth Paramhans (shared with S. Lodha)
6. Piyush Bhatt (shared with S. Lodha)
7. Bhaskar Das (shared S Lodha and A Laha)
8. Sangya Dutta (shared S Lodha and A Laha)

Post Doctoral Scholars

1. Dr Ravichandra Raju (Ph.D. from IIT Madras)

1. Sunny Sadana graduated with M. Tech. 2011 Process Integration Engineer at Global Foundries, Singapore (with S Lodha and Anil KG)
2. Shashank Gupta graduated with M. Tech. 2011 Research Engineer at Applied Materials, India and now in the Stanford Ph.D. program (with S Lodha)
3. Pranil Bafna graduated with M. Tech. 2012 Business Analyst at Inductis, Gurgaon, India (with S Lodha)
4. Prateek Karkare graduated with M. Tech 2012 Engineer at NVIDIA, Bangalore, India (with S Lodha)
5. Gurudatt Rao graduated with M. Tech in 2012 Engineer at TSMC, Taiwan (with N Venkatramani)
6. Dr V. S. Senthil Srinivasan (Ph.D. from DRDO Jodhpur)- presently at U. of Stuttgart

• April 2010-June 2010 Member of Technical Staff, FEP- Applied Materials
• Sept 2006- April 2010 Senior Application Development Engineer, FEP- Applied Materials,

• Technical Lead for Non-Volatile Flash Memory program
• Floating gate Flash gate-stack process integration and device engineering
• Process optimization for Charge Trap Flash Gate Stack for sub-40nm node NAND
• Technical Lead for NVM Joint Development Program with IMEC
• Technical Lead for university collaborations with IIT Bombay for NVM performance and reliability

• May 2007- Oct 2007 Visiting Assistant Professor, Electrical Engineering, IIT Bombay

• Nitride engineering (SiN-SiON-SiN) in Charge Trap Flash for endurance enhancement
• Simulation of number and position fluctations metal nanocrystal impact on memory scalability.

• May 2006- Aug 2006 Post Doctoral Scholar, NASA Ames Research Center

• NW based electronics (high mobility materials for logic, phase change memory and systems)

• Fall, 2004, Graduate Research Intern, Intel Research, Manager: Dr. Yuegang Zhang

• Carbon Nanotube based Flash memory based on metal nanocrystal charge storage

• 2003-2006 Research Assistant, Ph.D. program, Advisor: Prof. Edwin C. Kan, ECE

• Memory device using fullerenes (e.g. C60) for charge storage in molecular orbitals in Flash
• Carbon nanotube as gate of MOSFET for CMOS scaling study and molecular sensor applications
• Charge injection and transport study between a 1D to a 0D mesoscopic electronic system
• Integration of CVD SiO2 and ALD HfO2 for room temperature devices using nanotubes and fullerenes in CMOS

• 2000-2002 Research Assistant, Ph.D. program, Advisor: Prof. J. Peter Krusius, ECE

• Seamlessly tiled microdisplay assembly technology for LCoS microdisplay
• Novel CMP based metallization process development for ultra-flat die for micro-optics
• Novel scheme for the fabrication ultra-planar, zero-dishing, large area aluminum micro-mirror array

• 1999-2000 Research Assistant, IIT Madras, India Advisor: Prof. P.K. Nair, Metallurgy

• Design and fabrication of electric arc chamber for the large scale production of single walled carbon nanotubes

Department of Electrical Engineering
IIT Bombay, Powai
Mumbai 400 076, India
Email: udayan[AT]ee.iitb.ac.in
Phone: (O) +91 22 2576 7698
Office room no: Nanoelectronics Bldg Rm 605
Fax:

To schedule appointments please check my Google Calendar for a free slot and send me an email