Udayan Ganguly

• Flash Memory materials and device optimization
• Nanocrystal, nanotubes, nanowires growth and device characterization
• Novel materials/process integration in CMOS platform
• Chemical and bio sensors
• Experimental device physics with modeling/design

• Ph.D. Materials Science and Engineering Cornell University, 2006
• M.S., Materials Science and Engineering Cornell University, 2005
• B. Tech., Metallurgical Engineering Indian Institute of Technology Madras (IITM), 2000

• April 2010-June 2010 Member of Technical Staff, FEP- Applied Materials
• Sept 2006- April 2010 Senior Application Development Engineer, FEP- Applied Materials,

• Technical Lead for Non-Volatile Flash Memory program
• Floating gate Flash gate-stack process integration and device engineering
• Process optimization for Charge Trap Flash Gate Stack for sub-40nm node NAND
• Technical Lead for NVM Joint Development Program with IMEC
• Technical Lead for university collaborations with IIT Bombay for NVM performance and reliability

• May 2007- Oct 2007 Visiting Assistant Professor, Electrical Engineering, IIT Bombay

• Nitride engineering (SiN-SiON-SiN) in Charge Trap Flash for endurance enhancement
• Simulation of number and position fluctations metal nanocrystal impact on memory scalability.

• May 2006- Aug 2006 Post Doctoral Scholar, NASA Ames Research Center

• NW based electronics (high mobility materials for logic, phase change memory and systems)

• Fall, 2004, Graduate Research Intern, Intel Research, Manager: Dr. Yuegang Zhang

• Carbon Nanotube based Flash memory based on metal nanocrystal charge storage

• 2003-2006 Research Assistant, Ph.D. program, Advisor: Prof. Edwin C. Kan, ECE

• Memory device using fullerenes (e.g. C60) for charge storage in molecular orbitals in Flash
• Carbon nanotube as gate of MOSFET for CMOS scaling study and molecular sensor applications
• Charge injection and transport study between a 1D to a 0D mesoscopic electronic system
• Integration of CVD SiO2 and ALD HfO2 for room temperature devices using nanotubes and fullerenes in CMOS

• 2000-2002 Research Assistant, Ph.D. program, Advisor: Prof. J. Peter Krusius, ECE

• Seamlessly tiled microdisplay assembly technology for LCoS microdisplay
• Novel CMP based metallization process development for ultra-flat die for micro-optics
• Novel scheme for the fabrication ultra-planar, zero-dishing, large area aluminum micro-mirror array

• 1999-2000 Research Assistant, IIT Madras, India Advisor: Prof. P.K. Nair, Metallurgy

• Design and fabrication of electric arc chamber for the large scale production of single walled carbon nanotubes

• Employee of the Quarter, Front End Products, Applied Materials 2010
• MRS Trophy Award for best manuscript in Symposium D (MRS Fall 2004, Boston)

• U. Ganguly, Y. Yokota, J. Tang, S. Thirupapuliyur, C. Olsen, S. Sun, T. W. Poon, W. Liu, J. Swenberg, V. Nguyen, S. Srinivasan, J. Newman, ‘Semiconductor devices suitable for narrow pitch applications and methods of fabrication thereof’ (20100062603)
• ‘Nanotube- and nanocrystal-based non-volatile memory’, Y. Zhang, U. Ganguly and E.C. Kan, Intel Corporation (20070064478)

• U. Ganguly, T. Guarini, D. Wellekens, L. Date, Y. Cho, A. Rothschild, J. Swenberg, “Impact of Top-Surface Tunnel-Oxide Nitridation on Flash Memory Performance and Reliability, " IEEE Electron Device Letters, 31, 123, 2010

• C. Sandhya, A. B. Oak, N. Chattar, A. S. Joshi, U. Ganguly, C. Olsen, S. M. Seutter, L. Date, R. Hung, J. Vasi, and S. Mahapatra, ‘Impact of SiN Composition Variation on SANOS Memory Performance and Reliability under NAND (FN/FN) Operation’, IEEE Transactions on Electron Devices, V.56, No.12, pp. 3123 - 3132, 2009.

• C. Sandhya, U. Ganguly, N. Chattar, C. Olsen, S. M. Seutter, L. Date, R. Hung, J. Vasi, and S. Mahapatra, “Effect of SiN on Performance and Reliability of Charge Trap Flash (CTF) Under Fowler Nordheim Tunneling Program/Erase Operation” IEEE Electron Device Letters, 30, 171, 2009.

• U. Ganguly, T.-H. Hou, E. C. Kan, ‘Enhanced Electrostatics for Low-Voltage Operations in Nanocrystal based Nanotube/Nanowire Memories’, IEEE Trans. Nanotechnology, 6, 22, 2007.

• T.-H. Hou, U. Ganguly, and E. C. Kan, ‘Fermi-Level Pinning in Nanocrystal Memories’, IEEE Electron Device Letters, 28, 103, 2007.

• T.-H. Hou, U. Ganguly, and E. C. Kan, ‘Programmable Molecular Orbital States of C60 from Integrated Circuits,’ Applied Physics Letters, 89, 253113, 2006.

• U. Ganguly, V. Narayanan, C. Lee, T.-H. Hou, E. C. Kan, ‘Three dimensional analytical modeling of nanocrystal memory electrostatics’, Journal of Applied Physics, 99, 114516 2006.

• T. -H. Hou, C. Lee, V. Narayanan, U. Ganguly, E. C. Kan, ‘Design Optimization of Metal Nanocrystal Memory—Part II: Gate-Stack Engineering’, IEEE Transactions on Electron Devices, 53, 3103, 2006.

• T. -H. Hou, C. Lee, V. Narayanan, U. Ganguly, E. C. Kan, ‘Design Optimization of Metal Nanocrystal Memory—Part II: Gate-Stack Engineering’, IEEE Transactions on Electron Devices, 53, 3095, 2006.

• U. Ganguly, E.C. Kan, Y. Zhang, ‘Carbon nanotube FET memory with charge storage in metal nanocrystal’, Applied Physics Letters, 87, 043108 (2005).

• C. Lee, U. Ganguly, V. Narayanan, T.-H Hou, and E. C. Kan, ‘Asymmetric Electric Field Enhancement in Nanocrystal Memories’, IEEE Electron Device Letters, 26, 879, 2005.

• J. Guo, E. C. Kan, U. Ganguly, Y. Zhang, ‘High Sensitivity and Non-Linearity of Carbon-Nanotube-Based Charge Sensors’, Journal of Applied Physics, 99, 084301 2006.

• U. Ganguly, J. P. Krusius, “Fabrication of Ultra-Planar Aluminum Mirror Array by Novel Encapsulation CMP for Micro-optics and MEMS applications” Journal of Electrochemical Society, 151, H232, 2004.

• U. Ganguly, J. P. Krusius, “Novel compensation CMP for low dishing and high global planarity for ultra-planar die applications in micro-optics and MEMS”, Thin Solid Films, 460,306, 2004.

• U. Ganguly, Y. Yokota, J. Tang, S. Sun, M. Rogers, M. Jin , K. Thadani, H. Hamana, G. Leung, B. Chandrasekaran, S. Thirupapuliyur, C. Olsen, V. Nguyen, S. Srinivasan, “Scalability Enhancement of FG NAND by FG Shape Modification,” International Memory Workshop, Seoul, 2010

• Sandhya C., U. Ganguly, K.K. Singh, P.K. Singh, R. Hung, C. Olsen, S. M. Seutter, G. Conti, K. Ahmed,N. Krishna, J. Vasi, and S. Mahapatra, ‘The Effect of Band Gap Engineering of the Nitride Storage Node on Performance and Reliability of Charge Trap Flash’, International Physics of Failure Analysis (IPFA), 2008
• Sandhya C., U. Ganguly, K.K. Singh, P.K. Singh, R. Hung, C. Olsen, S. M. Seutter, G. Conti, K. Ahmed,N. Krishna, J. Vasi, and S. Mahapatra, ‘Nitride engineering and the effect of interfaces on Charge Trap Flash performance’, Internation Reliability Physics Symposium (IRPS), 2008

• A. Nainani, S. Palit, P. K. Singh, U. Ganguly, N. Krishna, J. Vasi and S. Mahapatra, ‘Development of A 3D Simulator for Metal Nanocrystal (NC) Flash Memories under NAND Operation’, International Electron Devices Meeting (IEDM) 2007.

• U. Ganguly, T.-H. Hou and E. C. Kan, ‘Process Integration of Composite High-k Tunneling Dielectric for Nanocrystal Based Carbon Nanotube Memory’, (MRS) Material Research Symposium, Boston, MA, Dec. 2006.

• U. Ganguly, T.-H. Hou and E. C. Kan, ‘Quantum Transport and Trap Effects in Tunneling Rate Measurements of Metal Nanocrystal Based Carbon Nanotube Memory’, (MRS) Material Research Symposium, Boston, MA, Dec. 2005.

• U. Ganguly, C. Lee and E. C. Kan, ‘Retention characteristics for nonvolatile memory based on metal nanocrystals and carbon nanotube FET with CVD SiO2 and ALD HfO2 tunneling dielectrics’, (MRS) Material Research Symposium, Boston, MA, Dec. 2005.

• U. Ganguly, J. Guo, E. C. Kan and Y. Zhang, ’Carbon nanotubes based non-volatile memory and charge sensors’, Proc. of SPIE Conference, vol. 6003, Oct., 2005. (Invited paper)

• U. Ganguly, C. Lee and E. C. Kan , ‘Experimental Observation of Non-Volatile Charge Injection and Molecular Redox in Fullerenes C60 and C70 in an EEPROM Type Device’, (MRS) Material Research Symposium, Boston, MA, Dec. 2004. MRS Trophy Award for best paper in Symposium D

• C. Lee, U. Ganguly and E. C. Kan, ‘Characterization of Number Fluctuations in Gate-last Metal Nanocrystal Nonvolatile Memory Array Beyond 90nm CMOS Technology’, (MRS) Material Research Symposium, Boston, MA, Dec. 2004.

• U. Ganguly, C. Lee and E. C. Kan, ‘Interface and oxide contamination monitoring in integration of fullerenes and carbon nanotubes with aggressively scaled CMOS gate stacks’, (MRS) Material Research Symposium, Boston, MA, Dec. 2003.

Department of Electrical Engineering
IIT Bombay, Powai
Mumbai 400 076, India
Email: udayan[AT]ee.iitb.ac.in
Phone: (O) +91 22 2576 7698
Office room no: EE 122D
Fax:
Calendar: To schedule appointments please check my Google Calendar, and send me an email