Juzer Vasi

• Silicon photovoltaic devices
• MOS insulators; high-k dielectrics; transport in MOS insulators; characterization of bulk and interface traps in these insulators
• Flash memory devices
• MOS device degradation and reliability: Study of hot-carrier effects, radiation effects, high-field stressing and breakdown in MOS devices
• MOS device modeling and simulation: Modeling and simulation of flash memory devices
• Nanoelectronics

• EE661 Physical Electronics
• EE620 Physics of Transistors
• EE733 Introduction to Solid State Devices
• EE112 Introduction to Electronics

• B.Tech., Indian Institute of Technology Bombay, 1969.
• Ph.D., The Johns Hopkins University, Baltimore, USA, 1973.

• 1st Batch P. K. Kelkar Chair Professor of Nanotechnology, Indian Institute of Technology Bombay, 2010-present
• Deputy Director, Indian Institute of Technology Bombay, 2006-2009
• Professor, Indian Institute of Technology Bombay, 1983-present
• Head, Department of Electrical Engineering, Indian Institute of Technology Bombay, 1992-1994
• Assistant Professor, Indian Institute of Technology Bombay, 1981-1983
• Lecturer & Assistant Professor, Indian Institute of Technology Delhi, 1974-1981
• Visiting Assistant Professor, The Johns Hopkins University, Baltimore, 1973-1974

• Fellow, IEEE
• Fellow, INAE
• Fellow, IETE
• Elected to The Johns Hopkins Society of Scholars, 1993
• Sreenivasan Memorial Award of IETE, for distinguished contributions to teaching of electronics in India, 1997
• Award for Excellence in Teaching, Indian Institute of Technology Bombay, 2000 and 2009
• Mathur Award for Excellence in Research, Indian Institute of Technology Bombay, 2006
• TechnoVisionary Award, India Semiconductor Association, 2008

Technical and Professional Contributions

• Over 120 papers published in journals and presented at international conferences
• Editor, IEEE Transactions on Electron Devices, 1996-2003
• Principal Investigator, National Centre for Photovoltaic Research & Education (NCPRE)
• Co-Principal Investigator, Centre of Excellence in Nanoelectronics (CEN)
• Co-Principal Investigator, Indian Nanoelectronics Users Programme (INUP)
• Investigator/co-investigator in funded projects from microelectronics industries like Motorola (USA), Siemens AG (Germany), National Semiconductor Corp. (USA), Renesas (Japan), Indian Telephone Industries, Bharat Electronics Ltd. (India), Semiconductor Complex Ltd. (India), etc.
• Member, Working Group on Technology of the National Microelectronics Council, Govt. of India, 1988-1994
• Member, Program Advisory Committee on Electrical, Electronics and Computer Engineering, Department of Science & Technology, Govt. of India, 1998-2003
• Member, Scientific Advisory Committee to the Cabinet (SAC-C), 2008-present

Professional Society Activities

• Editor, IEEE Transactions on Electron Devices, 1996-2003
• Distinguished Lecturer of the IEEE Electron Devices Society, 2001-2005
• Founding Chairman, IEEE APS/EDS Bombay Chapter, 1999-2000
• Chairman, IEEE Bombay Section, 2001-2002
• Chairman, IEEE Asia-Pacific Regions/Chapters Subcommittee, 2005-2006
• Guest Editor, Journal of IETE Special Issue on Microelectronics, 1990

Department of Electrical Engineering
IIT Bombay, Powai
Mumbai 400 076, India
Email : vasi[AT]ee.iitb.ac.in
Phone (Office) : (0091 22) - 2576 7408
Office room no: A-205
Fax: (0091 22) - 25723707

Journal Publications

1. N.Bhat and J.Vasi, “Interface-state generation under radiation and high-field stressing in RNO MOS capacitors,” IEEE Trans. Nucl. Sci. 39, 2230 (1992).
2. R.M.Patrikar, R.Lal and J.Vasi, “Power law model for positive charge buildup in silicon dioxide due to high-field stressing,” Solid-St. Electron. 36, 723 (1993).
3. A.Mallik, J.Vasi and A.N.Chandorkar, “The nature of hole traps in RNO gate dielectrics,” J. Appl. Phys. 74, 2665 (1993).
4. R.M.Patrikar, R.Lal and J.Vasi, “Net positive charge buildup in various MOS insulators due to high-field stressing,” IEEE Electron Device Lett. 14, 530 (1993).
5. V.Vasudevan and J.Vasi, “A two-dimensional numerical simulation of oxide charge build up in MOS transistors due to radiation,” IEEE Trans. Electron Devices 41, 383 (1994).
6. R.M.Patrikar, R.Lal and J.Vasi, “Interface-state generation due to high-field stressing in MOS oxides,” Solid-St. Electron. 38, 477 (1995).
7. V. Ramgopal Rao, D.K. Sharma and J. Vasi, “Neutral electron trap generation under irradiation for RNO gate dielectrics,” IEEE Trans. Electron Devices 43, 1467 (1996).
8. P.V.S. Subrahmanyam, A. Prabhakar and J. Vasi, “High-field stressing effects on the split N2O grown thin gate dielectrics by rapid thermal processing,” IEEE Trans. Electron Devices 44, 505 (1997).
9. S. Mahapatra, C. D. Parikh and J. Vasi, “A new ‘multifrequency’ charge pumping technique to profile hot-carrier induced interface-state density in nMOSFETs,” IEEE Trans. Electron Devices 46, 960 (1999).
10. S. Mahapatra, C. D. Parikh, V. Ramgopal Rao, C. R. Vishwanathan and J. Vasi, “A comprehensive study of hot-carrier induced interface and oxide trap distributions in MOSFETs using a novel charge pumping technique,” IEEE Trans. Electron Devices 47, 171 (2000).
11. S. Mahapatra, V. Ramgopal Rao, B. Cheng, M. Khare, C. D. Parikh, J. C. S. Woo and J. Vasi, “Performance and Hot-Carrier Reliability of 100 nm Channel Length Jet Vapor Deposited Si3N4 MNSFETs”, IEEE Trans. on Electron Devices 48, 679 (2001).
12. S. Mahapatra, V.Ramgopal Rao, J. Vasi, B.Cheng, J.C.S.Woo, “A Study of Hot-Carrier Induced Interface-Trap Profiles in Lateral Asymmetric Channel MOSFETs Using a Novel Charge Pumping Technique”, Solid-State Electronics 45, 1717 (2001).
13. Najeeb-ud-din, Mohan V. Dunga, Aatish Kumar, J.Vasi, V.Ramgopal Rao, Baohong Cheng, J.C.S.Woo, “Analysis of Floating Body Effects in Thin Film Conventional and Single Pocket SOI MOSFETs using the GIDL Current Technique,” IEEE Electron Device Letters 23, (2002).
14. K.N.Manjularani, V. R. Rao and J. Vasi, “A New Method to Characterize Border Traps in Sub-Micron Transistors using Hysteresis in the Drain Current,” IEEE Transactions on Electron Devices 50, 973 (2003).
15. A. S. Roy, J. Vasi, and M. B. Patil, “A new approach to model Non-Quasi-Static (NQS) effects in MOSFET’s Part I: Large-signal analysis,” IEEE Trans. Electron Devices 51, (2004).
16. A. S. Roy, J. Vasi, and M. B. Patil, “A new approach to model Non-Quasi-Static (NQS) effects in MOSFET’s Part II: Small-signal analysis,” IEEE Trans. Electron Devices, 51, (2004).
17. K.N.Manjularani, V. R. Rao and J. Vasi, “Stress voltage polarity dependence of JVD Si3N4 MNSFET degradation,” IEEE Trans. Device and Materials Reliability, 4, (2004).
18. P. Jain, J. Vasi and R. Lal, “SEU Reliability - Study of advanced deep sub-micron transistors,” IEEE Trans. Device and Materials Reliability, 5, (2005).
19. S. N. Agarwal, A. Jha, D. Vinay Kumar, J. M. Vasi, M. B. Patil, S. C. Rustagi, “Look-up Table Approach for RF Circuit simulation Using a Novel Measurement Technique,” IEEE Transactions on Electron Devices 52, 973 (2005).
20. V. Hariharan, J. Vasi and V. R. Rao, “Drain current model including velocity saturation for symmetric double-gate MOSFETs,” IEEE Transactions on Electron Devices 55, (2008).
21. V. Hariharan, J. Vasi and V. Ramgopal Rao, “An improvement to the numerical robustness of the surface potential approximation for double-gate MOSFETs,” IEEE Transactions on Electron Devices 56, 529 (2009).
22. C. Sandhya, U. Ganguly, N. Chattar, C. Olsen, S. M. Seutter, L. Date, R. Hung, J. Vasi, and S. Mahapatra, “Effect of SiN on Performance and Reliability of Charge Trap Flash (CTF) Under Fowler Nordheim Tunneling Program/Erase Operation”, Electron. Device Lett., 30, 171 (2009).

International Conference Papers

1. A.Mallik, A.N.Chandorkar and J.Vasi, “Electron trapping during irradiation in RNO,” 30th IEEE Nuclear and Space Radiation Effects Conference, Snowbird, USA (1993).
2. R.M.Patrikar, R.Lal and J.Vasi, “Physical models for electron trap generation in MOS oxides stressed at high fields,” 7th International Workshop on the Physics of Semiconductor Devices, New Delhi (1993).
3. S.Ekbote, D. Tambe, P. Zaman, H.K. Dangat, M.Khare, P.Sinha, S.Rodd, N.Bhukhanwala, J.Vasi, D.K. Sharma and A.Das, “Simulation of radiation effects in MOSFETs,” 8th International Workshop on the Physics of Semiconductor Devices, New Delhi (1995).
4. K.G. Anil, J. Vasi and R. Lal, “ Low-dose radiation sensor for radiation therapy dosimetry,” 9th International Workshop on the Physics of Semiconductor Devices, New Delhi (1997).
5. S. Mahapatra, V. Ramgopal Rao, K. N. ManjulaRani, C. D. Parikh, J. Vasi, B. Cheng, M. Khare and J. C. S. Woo, “100 nm channel length MNSFETs using a Jet Vapor Deposited ultra-thin silicon nitride gate dielectric,” Int. Symposium on VLSI Technology, Kyoto, Japan (1999).
6. S. Mahapatra, V. Ramgopal Rao, C. D. Parikh, J. Vasi, B. Cheng and J. C. S. Woo, “A study of 100 nm channel length asymmetric MOSFET by using charge pumping,” Int. Conf. on Insulating Films on Semiconductors (INFOS ‘99), Erlangen, Germany (1999).
7. S. Mahaptra, V. Ramgopal Rao, C. D. Parikh, J. Vasi, B. Cheng, M. Khare and J. C. S. Woo, “Hot-carrier induced interface-state degradation in JVD SiN MNSFETs as studied by a novel charge pumping technique,” 29th European Solid-State Device Research Conference (ESSDERC 99), Leuven, Belgium (1999).
8. A. Topkar, S. Lodha, A. T. Mahfooz, R. Lal, J. Vasi and L. Nanver, “Ionizing radiation induced degradation of SiGe HBTs,” 10th Int. Workshop on Physics of SemiconductorDevices, New Delhi (1999).
9. K. G. Anil, S. Mahapatra, I. Eisele, V. R. Rao and J. Vasi, “Drain bias dependence of gate oxide reliability in conventional and asymmetrical channel MOSFETs,” 30th European Solid-State Device Research Conference (ESSDERC 2000), Cork, Ireland (2000).
10. V. Ramgopal Rao, S. Mahapatra, and J.Vasi, K. G. Anil, C. Fink, W. Hansch and I. Eisele, “Hot-carrier performance of 60 nm channel length delta-doped vertical MOSFETs with high-pressure grown oxide as a gate dielectric” 31st IEEE Semiconductor Interface Specialists Conference (SISC 2000), San Diego, California (2000).
11. A. Khamesra, R. Lal , J. Vasi, A. Kumar K. P. and J. K. O. Sin, “Device degradation of n-channel poly-Si TFT’s due to high-field, hot-carrier and radiation stressing,” 8th International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA 2001), Singapore (2001).
12. Najeeb-ud-Din, M. V. Dunga, Aatish Kumar, V. Ramgopal Rao and J. Vasi, “Characterization of Lateral Asymmetric Channel (LAC) Thin Film SOI MOSFETs,” Sixth International Conference on Solid-State and Integrated-Circuit Technology (ICSICT 2001), Shanghai, China (2001).
13. K. N. ManjulaRani, V. Ramgopal Rao and J. Vasi, “Border trap characterization in ultra-thin JVD nitride capacitors,” 32nd IEEE Semiconductor Interface Specialists Conference (SISC 2001), Washington, DC (2001).
14. D. R. Nair, M. B. Patil and J. Vasi, “Extraction of effective mass of carriers in Si3N4 by accurate modeling of gate tunneling current,” 32nd IEEE Semiconductor Interface Specialists Conference (SISC 2001), Washington, DC (2001).
15. Najeeb-ud-Din, Aatish Kumar, Mohan V.Dunga, V.Ramgopal Rao, J.Vasi, “Suppression of Parasitic BJT Action in Single Pocket Thin Film Deep Sub-micron SOI MOSFETs,” 2002 MRS Spring Meeting, San Francisco, California (2002).
16. K. N. ManjulaRani, V. Ramgopal Rao and J. Vasi, “Degradation Study of Ultra-Thin JVD Silicon Nitride MNSFET,” 2002 MRS Spring Meeting, San Francisco, California (2002).
17. K. N. ManjulaRani, V. Ramgopal Rao and J. Vasi, “Characterization of high-field stress-induced border traps in JVD Si3N4 transistors by drain current transient and 1/f methods,” 34th IEEE Semiconductor Interface Specialists Conference (SISC 2003), Washington, DC (2003).
18. K. N. ManjulaRani, V. Ramgopal Rao and J. Vasi, “Reliability of ultra-thin JVD silicon nitride MNSFETs under high-field stressing,” 10th International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA 2003), Singapore (2003).
19. A. Jha, J. Vasi, S. C. Rustagi and M. B. Patil, “A novel method to obtain 3-port network parameters for a MOSFET from 2-port measurements,” International Conference on Microelectronic Test Structures, Hyogo, Japan (2004).
20. P. Jain, J. Vasi and R. Lal, “Single-event-induced barrier lowering in deep sub-micron CMOS devices and circuits,” 11th International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA 2004), Taiwan (2004).
21. P. Bharath Kumar, Ravinder Sharma, Pradeep R. Nair, Deleep R. Nair, S. Kamohara, S. Mahapatra, and J. Vasi, “Mechanism of Drain Disturb in SONOS Flash EEPROMs,” International Reliability Physics Symposium (2005).
22. P. Jain, D. V. Kumar, J. Vasi and M. B. Patil, “Evaluation of non-quasi-static effects during SEU in deep submicron MOS devices and circuits,” Proceedings of the 19th International Conference on VLSI Design (VLSI’06) (2006).
23. A. Nainani, S. Palit, P. K. Singh, U. Ganguly, N. Krishna, J. Vasi and S. Mahapatra, “Development of a 3D simulator for metal nanocrystal flash memories under NAND operation,” International Electron Devices Meeting (IEDM) (2007).
24. Sandhya C., U. Ganguly, K.K. Singh, P.K. Singh, C. Olsen, S. M. Seutter, R. Hung, G. Conti, K. Ahmed, N. Krishna, J. Vasi and S. Mahapatra, “Nitride Engineering and the effect of interfaces on charge trap flash performance and reliability,” International Reliability Physics Symposium (IRPS) (2008).