Abstract: The basic physics of ESD phenomenon and its relevance for semiconductor industry is explained. On-chip ESD protection measures including the relevant design parameters are discussed. It is shown, how TCAD and circuit simulations are supporting the optimization of the ESD protection devices. As advanced CMOS ICs do not only require optimized ESD protection devices but also need a careful choice of supply net to survive ESD events, advantageous supply concepts are presented. An outlook is given for the challenges of ESD protection for GigaHertz circuits and process technologies using non planar devices (e.g. FINFET).