Madhav P. Desai received the B.Tech. in Electrical engineering from IIT Bombay in 1984, and the M. S. and Ph.D. degrees from the University of Illinois at Urbana-Champaign.  During the period 1992-1996, he worked in the Semiconductor Engineering Group at the Digital Equipment Corporation in Hudson, MA, where he was a Principal Engineer.  He is currently an Associate Professor in the Department of Electrical Engineering at IIT Bombay.  Dr. Desai's interests are in the areas of VLSI design and design tools, circuits and systems, and combinatorial algorithms. His doctoral work involved the study of the Simulated Annealing algorithm, which is a popular combinatorial optimization technique. While at Digital, Dr. Desai worked on timing verification, delay modeling, circuit and interconnect optimization and contributed to the design of two of the world's fastest CMOS microprocessors.  Dr. Desai has been the recipient of GTE and Schlumberger Graduate Fellowships. He has served as a reviewer for the IEEE Transactions on Circuits and Systems, the IEEE Transactions on Computers, the SIAM Journal on Control, and various conferences.