| H. Narayanan |
H.Narayanan did his B.Tech. and Ph.D. from IIT Bombay. He has been a faculty member with the Electrical Engineering Department at IIT Bombay since 1974. He was a visiting faculty with the EECS Department at UC Berkeley, Berkeley, California during 1983-1985. Dr. Narayanan's primary interests are in the area of Electrical Network Analysis - particularly in the use of topological methods for the efficient analysis of networks. He has supervised the building of the general purpose circuit simulator BITSIM, which uses such methods. BITSIM permits the option of using the Conjugate gradient method for solution of the linear equations which arise during circuit simulation. He is also interested in VLSI optimization problems such as partitioning where he applies the theory of submodular functions to produce efficient partitioners. He has participated in the building of VLSI circuit partitioners (related to realization through FPGAs) for industries in the US and in Japan. He is the author of the recently published monograph, Submodular Functions and Electrical Networks (North Holland, 1997).
email:hn@ee.iitb.ernet.in