V.Ramgopal Rao:Publications::

RESEARCH PUBLICATIONS:

INTERNATIONAL JOURNALS:

Mayank Gupta, V.Vidya, V.Ramgopal Rao, Kun H. To, J.C.S.Woo, "Optimization of Sub-100 nm Gamma-gate Si-MOSFETs for RF Applications", Wireless Design and Development magazine (Featured Technology Article), December 2005 (Invited)

Neeraj K. Jha, P. Sahajananda Reddy, D.K. Sharma and V. Ramgopal Rao, "NBTI Degradation and its Impact for Analog Circuit Reliability", IEEE Transactions on Electron Devices,pp. 2609-2615, December 2005

Amarchand Sathyapalan, Anup Lohani, Sangita Santra, Saurabh Goyal, M. Ravikanth, Soumyo Mukherj, V. Ramgopal Rao, "Preparation, characterization and electrical properties of a novel self-assembled meso-pyridyl pophyrin monolayer on gold surfaces", Australian Journal of Chemistry, Vol.58, pp. 810-816, 2005

Neeraj K.Jha, V.Ramgopal Rao, "A New Oxide Trap Assisted NBTI Degradation Model", IEEE Electron Device Letters, Volume: 26, Issue: 9, September 2005, pp.687-689

M. V. Rammohan Reddy, D. K. Sharma, M.B.Patil and V. Ramgopal Rao, "Power-Area Evaluation of Various Double-Gate RF Mixer Topologies", IEEE Electron Device Letters, Volume: 26, Issue: 9, June 2005, pp.664 – 666

D. V. Kumar, K.Narasimhulu, P. S. Reddy, M.Shojaei, D. K. Sharma, M. B. Patil, V.Ramgopal Rao, "Evaluation of the Impact of Layout on Device and Analog Circuit Performance with Lateral Asymmetric Channel MOSFETs", IEEE Transactions on Electron Devices, Volume 52, Issue 7, July 2005 Pages:1603 - 1609

Najeeb-ud-din, V.Ramgopal Rao, J.Vasi, "Design of 0.1 um single halo (SH) thin film silicon-on-insulator (SOI) MOSFETs for analog applications", Semiconductor Science and Technology, vol. 20, p.895-902, 2005 (IOP Publishing Ltd, UK)

Najeeb-ud-din, V.Ramgopal Rao, J.Vasi, and J.C.S.Woo, "Superior Hot Carrier Reliability of Single Halo (SH) Silicon-on-Insulator (SOI) nMOSFET in Analog Applications", IEEE Transactions on Device and Materials Reliability, Volume 5, Issue 1, Pages: 127 - 132, 2005

Pradeep Kumar Chawda, Bulusu Anand, and V. Ramgopal Rao, "Optimum Body Bias Constraints for Leakage Reduction in High–K CMOS Circuits", Accepted for publication, Japanese Journal of Applied Physics, 2005

K. Narasimhulu, V. Ramgopal Rao, "Deep Sub-micron Device and Analog Circuit Parameter Sensitivity to Process Variations with Halo Doping and Its Effect on Circult Linearity", Accepted for publication, Japanese Journal of Applied Physics, 2005

K. Narasimhulu, Madhav P. Desai, Siva G. Narendra and V. Ramgopal Rao, "The Effect of Lateral Asymmetric Channel (LAC) Doping on Deep Sub-micron Transistor Capacitances and its Influence on Device RF Performance", IEEE Transactions on Electron Devices, Volume: 51, Issue: 9, Sept. 2004, pp. 1416 – 1423

B.Anand, M.P.Desai, and V.Ramgopal Rao, "Silicon Film Thickness Optimization for SOI-DTMOS from Circuit Performance considerations", IEEE Electron Device Letters, Volume: 25, Issue: 6 , June 2004, pp.436 – 438

K.N.Manjularani, V.Ramgopal Rao, J.Vasi, "Reliability of Ultrathin JVD Silicon Nitride MNSFETs under High Field Stressing" IEEE Transactions on Device and Materials Reliability, Vol.4,pp.18 - 23, March 2004

V.Ramgopal Rao, Nihar R. Mohapatra, "Device and Circuit Performance issues with Deeply Scaled High-K MOS Transistors", Journal of Semiconductor Technology and Science (JSTS), Korea, Special issue on Scaled Nano Devices, pp.52-62, Vol. 4, No. 1, March,2004.(Invited)

Samadhan B. Patil, Anand V. Vairagar, Alka A. Kumbhar, Laxmi K. Sahu, V. Ramgopal Rao, N. Venkatramani, R. O. Dusane and B. Schroeder, “Highly Conducting P+- PolySi Deposited by HWCVD and its Applicability As Gate Material for CMOS Devices” Thin Solid Films, Vol.430, 2003, pp.63-66

Nihar R. Mohapatra, Madhav P. Desai, Siva.G.Narendra, V. Ramgopal Rao, “Modeling of Parasitic Capacitances in Deep Sub-micrometer Conventional and High-K dielectric MOS Transistors” IEEE Transactions on Electron Devices, vol. 50, No.4, pp. 959-966, 2003

K.N.Manjularani, V.Ramgopal Rao, and J.Vasi, "A New Method to Characterize Border Traps in Sub-Micron Transistors using Hysteresis in the Drain Current", IEEE Transactions on Electron Devices, vol. 50, No.4, pp. 973-979, 2003

Parag C. Waghmare, Samadhan B. Patil, Alka A. Kumbhar, Laxmi Sahoo, V. Ramgopal Rao, and R.O. Dusane, “Nitrogen dilution effects on structural and electrical properties of hot wire deposited a-SiN:H films for Deep Sub-micron CMOS Technologies”, Thin Solid Films, Vol.430, 2003, pp.189-191

N.R.Mohapatra, D.R.Nair, S.Mahapatra, V.Ramgopal Rao, S.Shukuri, J.D.Bude, "CHISEL programming Operation of Scaled NOR Flash EEPROMs-Effect of Voltage Scaling, Device Scaling, and Technological Parameters", IEEE Transactions on Electron Devices, vol. 50, pp.2104-2111, October 2003

K.Narasimhulu, D.K.Sharma and V.Ramgopal Rao, "Impact of Lateral Asymmetric Channel Doping on Deep Sub-Micrometer Mixed-Signal Device and Circuit Performance", IEEE Transactions on Electron Devices vol. 50, pp.2481-2489, December 2003

Parag C.W, Samadhan Patil, Alka Kumbhar, R.O.Dusane, V.Ramgopal Rao, “Ultra thin Silicon Nitride by Hot Wire CVD for Deep Sub-Micron CMOS Technologies”, Microelectronic Engineering, Vol. 61-62, p. 625-629, 2002

Najeeb-ud-din, Mohan V. Dunga, Aatish Kumar, J.Vasi, V.Ramgopal Rao, Baohong Cheng, J.C.S.Woo, “Analysis of Floating Body Effects in Thin Film Conventional and Single Pocket SOI MOSFETs using the GIDL Current Technique”, IEEE Electron Device Letters, vol. 23, p. 209-211, April 2002

D.G.Borse, Manjula Rani K.N., Neeraj K. Jha, A.N. Chandorkar, J.Vasi, V. Ramgopal Rao, B.Cheng, J.C.S. Woo, "Optimization and Realization of Sub 100nm Channel Length Single Halo p-MOSFETs" IEEE Transactions on Electron Devices, vol.49, (no.6), June 2002.

Nihar R. Mohapatra, Madhav P. Desai, Siva G. Narendra, V. Ramgopal Rao, "The Effect of High-K Gate Dielectrics on Deep Sub-micrometer CMOS Device and Circuit Performance" IEEE Transactions on Electron Devices, vol.49, (no.5), May 2002, p.826- 831

Shantanu Rastogi, Ritesh Jhaveri, S.Mukherji, M.Ravikanth, and V.Ramgopal Rao, “Status and Trends in Molecular Electronics”, Special issue of IETE Technical Review on Nano Technology, Volume 19, No.5, pp 305-313, October 2002 (Invited)

Abhay Porwal, Mayur Narsude, Soumyo Mukherji, and V.Ramgopal Rao, “Microcantilever Based Biosensors”, Special issue of IETE Technical Review on Nano Technology, Volume 19, No.5, pp 293-303, October 2002 (Invited)

S. Mahapatra, V. Ramgopal Rao, B. Cheng, M. Khare, C. D. Parikh, J. C. S. Woo and J. Vasi, "Performance and Hot-Carrier Reliability of 100 nm Channel Length Jet Vapor Deposited Si3N4 MNSFETs", IEEE Transactions on Electron Devices, vol.48, (no.4), April 2001. p.679-84

S. Mahapatra, V.Ramgopal Rao, B.Cheng, J.Vasi and J.C.S.Woo "A Study of Hot-Carrier Induced Interface-Trap Profiles in Lateral Asymmetric Channel MOSFETs Using a Novel Charge Pumping Technique", Solid State Electronics, Vol. 45, p.1717-1723, 2001

Nihar.R.Mohapatra, A.Dutta, G.Sridhar, M.P.Desai and V.Ramgopal Rao “Sub 100 nm CMOS Circuit Performance with High-K Gate Dielectrics” Microelectronics Reliability, Vol. 41, p.1045-1048, 2001

Aatish Kumar, Souvik Mahapatra, Rakesh Lal, and V. Ramgopal Rao, “Multi-Frequency Transconductance Technique for Interface Characterization of Deep Sub-Micron SOI-MOSFETs”, Microelectronics Reliability, Vol. 41, p. 1049-1051, 2001

Samadhan B.Patil, A.Kumbhar, P.Waghmare, V.Ramgopal Rao, and R.O.Dusane, “Low Temperatue Silicon Nitride deposited by Hot-Wire CVD for Deep Sub-micron CMOS Devices”, Thin Solid Films, Vol. 395, p 270-274, 2001

Aatish Kumar, Rakesh Lal, and V. Ramgopal Rao, “A Simple and Direct Technique for Interface Characterization of SOI MOSFETs and its Application in Hot Carrier Degradation Studies in Sub 100 nm JVD MNSFETs”, Microelectronic Engineering, Vol. 59, p. 429-433, 2001

Kottantharayil Anil, Souvik Mahapatra, V.Ramgopal Rao and I. Eisele, “Comparison of Sub-Bandgap Impact Ionization in Sub-100 nm Conventional and Lateral Asymmetrical Channel nMOSFETs”, Japanese Journal of Applied Physics, Vol. 40 (2001) 2621-2626, Part 1, No. 4B, 30 April 2001

S.Mahapatra, C.D.Parikh, V.Ramgopal Rao, C.R.Viswanathan, and J.Vasi, "A Comprehensive study of hot-carrier induced interface and oxide trap distributions in MOSFETs using a novel charge pumping technique", IEEE Transactions on Electron Devices, vol. 47, p. 171-178, January, 2000

S.Mahapatra, C.D.Parikh, V.Ramgopal Rao, C.R.Viswanathan, and J.Vasi, "Device Scaling Effects on Hot-Carrier Induced Interface and Oxide Trap Distributions in MOSFETs", IEEE Transactions on Electron Devices, vol. 47, p. 789-796, April 2000

B.Cheng, V.Ramgopal Rao and J.C.S.Woo, “Exploration of Velocity Overshoot in a High-Performance Deep sub 100 nm SOI MOSFET with Asymmetric Channel Profile” IEEE Electron Device Letters, vol. 20, p. 538-540, October 1999

B.Cheng, M.Cao, V.Ramgopal Rao, A.Inani, P.V.Voorde, W.Greene, Z.Yu, H.Stork, and J.C.S.Woo, “The impact of high-k gate dielectrics and metal gate electrode on sub 100 nm MOSFETs”, IEEE Transactions on Electron Devices, vol. 46, p. 1537, 1999

A.Inani, V.Ramgopal Rao, B.Cheng, and J.C.S. Woo, “Gate Stack Architecture Analysis and Channel Engineering in Deep Sub-Micron MOSFETs”, Japanese Journal of Applied Physics, Part 1, April 1999, vol.38, (no.4B): p. 2266-71

S.Mahapatra, C.D.Parikh, J.Vasi, V.Ramgopal Rao, and C.R.Viswanathan, “A Direct Charge Pumping Technique for Spatial Profiling of Hot-Carrier Induced Interface and Oxide Traps in MOSFETs”, Solid State Electronics, p. 915, vol. 43, 1999

V. Ramgopal Rao, W.Hansch, S. Mahaptra, D.K. Sharma, J.Vasi, T.Grabolla, and I.Eisele, “Low Temperature-High Pressure Grown Thin Gate Dielectrics for MOS Applications” Microelectronic Engineering, vol. 48, p.223-226, 1999

S. Mahapatra, V. Ramgopal .Rao, C.D.Parikh, J.Vasi, B.Cheng, and J.C.S.Woo, "A Study of 100 nm Channel Length Asymmetric MOSFETs by Using Charge Pumping", Microelectronics Engineering, vol. 48, p. 193-196, 1999

W.Hansch, V.Ramgopal Rao, C.Fink, F.Kaesen, and I.Eisele, "Electric Field Tailoring in MBE Grown Vertical Sub-100 nm MOSFETs", Thin Solid Films, vol..321, p. 206-214, 1998

T.Brozek, V. Ramgopal Rao, A.Sridharan, J. Werking, D.Chan, and C.R.Viswanathan, "Charge Injection using Gate-Induced-Drain-Leakage Current for Characterization of Plasma Edge Damage in CMOS Devices" IEEE Transactions on Semiconductor Manufacturing, vol. 11 (2), May 1998

C.R. Viswanathan, and V. Ramgopal Rao "Application of charge pumping technique for sub-micron MOSFET characterization" Microelectronic Engineering, vol.40, (no.3-4):p. 131-46, Nov. 1998

A.Balandin, S.Cai, R.Li, K.L.Wang, V.Ramgopal Rao, and C.R.Viswanathan, "Flicker Noise in GaN/Al0.15Ga0.85N Doped Channel Heterostructure Field Effect Transistors", IEEE Electron Device Letters, p. 475, Vol. 19, 1998

V. Ramgopal Rao, W. Hansch, H. Baumgartner, I. Eisele, D. K. Sharma and J. Vasi "Charge Trapping Behavior in Deposited and Grown Oxides", Thin Solid Films, vol. 296, p. 37, 1997

V. Ramgopal Rao, I. Eisele, R. M. Patrikar, D. K. Sharma, J. Vasi, and T. Grabolla "High-Field Stressing of LPCVD Gate Oxides", IEEE Electron Device Letters, vol.18, p.84, 1997

V. Ramgopal Rao, F. Wittmann, H. Gossner, and I. Eisele, " Hysteresis Behaviour in 85 nm Channel Length Vertical MOSFETs Grown by MBE", IEEE Trans. on Electron Devices, vol. 43(6), p. 973, 1996

V. Ramgopal Rao, D. K. Sharma, and J. Vasi, "Neutral Electron Trap Generation under Irradiation in Reoxidised Nitrided oxide Gate Dielectrics", IEEE Trans. on Electron Devices, vol. 43, p. 1467, 1996

V. Ramgopal Rao and J. Vasi, "Radiation induced interface state generation in reoxidised nitrided oxides", Journal of Applied Physics, 71(2), 1992

INTERNATIONAL CONFERENCE PROCEEDINGS:

Manoj C.R, Abhinav Mangal, V.Ramgopal Rao, Hiroshi Iwai,"Parasitic Effects in Multi-gate MOSFETs", International Workshop on Nano CMOS, Jan 30- Feb 1, 2006, Mishima, Shizuoka prefecture, Japan (Invited)

K. Narasimhulu and V. Ramgopal Rao, "Analog Device and Circuit Performance Degradation under Substrate Enhanced Hot Carrier Stress Conditions", Accepted for Oral presentation, 2006 (44th Annual) International Reliability Physics Symposium (IRPS), March 26-30, 2006, San Jose, California, USA

Partha Sarkar, A.Mallik, C.K.Sarkar, V.Ramgopal Rao, "Performance of Channel Engineered SDODEL MOSFET for Mixed Signal Applications", Accepted, 2005 IEEE International Conference on Electron Devices and Solid-State Circuits, Hong Kong, December 19-21, 2005

K.Narasimhulu, V.Ramgopal Rao, "Analog Circuit Performance Issues with Aggressively Scaled
Gate Oxide CMOS Technologies", Accepted for presentation, 19 th International Conference on VLSI Design, January 3 - 7, 2006, Hyderabad, India

M.V.Rammohan Reddy, D.K.Sharma,M.B.Patil, V.Ramgopal Rao, "Multigate FETs for sub 65nm CMOS Technologies- Implications for Circuit Design", 13 th International Workshop on The Physics of Semiconductor Devices (IWPSD), December 13-17, 2005, New Delhi (Invited)

K.Narasimhulu, V.Ramgopal Rao,"Forward Body-biased Single Halo MOS Devices for Low Voltage Analog Circuits", Proceedings of the 2005 International Conference on Simulation of Semiconductor Processes and Devices, September 1-3, 2005, Tokyo, Japan

A. Sathyapalan, A. Lohani, Sangita Santra, M. Ravikanth, S.Mukherji, V.Ramgopal Rao, "Meso-pyridyl Porphyrin Self-assembled Monolayers on Gold Substrates for Molecular Electronics Applications", Proceedings of the 5 th IEEE Conference on Nanotechnology, July 11-15,Nagoya, Japan

M. Joshi, R.Pinto, V.Ramgopal Rao, S.Mukherji, “Silanization and Antibody Immobilization on SU8”, Proceedings of the 3rd International Conference on Materials for Advanced Technologies (ICMAT 2005), 3 - 8 July 2005, Singapore

Neeraj K. Jha, P. Sahajananda Reddy and V.Ramgopal Rao, "A New Drain Voltage Enhanced NBTI Degradation Mechanism", Proceedings of the 2005 (43 rd Annual) International Reliability Physics Symposium (IRPS), April 17 – 21, 2005, San Jose, California, USA

M.Joshi, S.Singh, B.Swain, S.Patil, R.Dusane, V.Ramgopal Rao, S.Mukherji, "Anhydrous silanization and antibody immobilization on hotwire CVD deposited silicon oxynitride films",
Proceedings of the IEEE INDICON 2004, Dec. 20-22, 2004 Pages:538 - 541

K. Narasimhulu, V. Ramgopal Rao, "Understanding the Impact of Process Variations on Analog Circuit Performance with Halo Channel Doped Deep Sub-Micron CMOS Technologies", Proceedings of the 35th International Conference on Solid State Devices and Materials (SSDM 2004), Tokyo, Japan, September 15-17, 2004

Pradeep Kumar Chawda, B. Anand, and V.Ramgopal Rao, "Effectiveness of Optimum Body Bias for Leakage Reduction in High K CMOS Circuits", Proceedings of the 35 th International Conference on Solid State Devices and Materials (SSDM 2004), Tokyo, Japan, September 15-17, 2004

M.Joshi, V.Ramgopl Rao, S.Mukherji, "AFM characterization and selectivity of immobilization of antibodies for Bio-MEMS applications" Proceedings of the International Bio-engineering Conference, September 8-10, 2004, Singapore

Bhawna Tomar, V. Ramgopal Rao, "Sub-threshold Swing Degradation due to Localized Charge Storage in SONOS Memories", Proceedings of the 11 th IEEE International Symposium on Physical and Failure Analysis of Integrated Circuits, July 5-8, 2004 Hinshcu, Taiwan

Neeraj Jha, V.Ramgopal Rao, "Understanding the NBTI Degradation in Halo- Doped Channel p-MOSFETs" Proceedings of the 11th IEEE International Symposium on Physical and Failure Analysis of Integrated Circuits, July 5-8, 2004 Hinshcu, Taiwan

V.Ramgopal Rao, "Nanotechnology-A revolution in progress", 'Electrical & Electronics' magazine, June, 2004 (Invited)

K. Narasimhulu,Siva G.Narendra, and V. Ramgopal Rao, “Effect of Process Variations on Device and Circuit Parameters with LAC/DH MOSFETs”, Proceedings of the 17 th IEEE International Conference on VLSI Design, January 7-9, 2004, Mumbai, India

A.Dixit, and V. Ramgopal Rao, “A Novel Dynamic Threshold Operation Using Electrically Induced Junction MOSFET in the Deep sub-micrometer CMOS Regime”, Proceedings of the 16th IEEE International Conference on VLSI Design, January 4-8, 2003,NewDelhi,India.

N.R Mohapatra, M.P.Desai, and V. Ramgopal Rao “Detailed Analysis of FIBL in MOS Transistors with High-K Gate Dielectrics”, Proceedings of the 16th IEEE International Conference on VLSI Design, January 4-8, 2003, New Delhi, India

D. Vinay Kumar, N. R.Mohapatra, V. Ramgopal Rao, and M. B. Patil, "Application of the look-up table approach to high-K dielectric MOS transistor circuits," Proceedings of the 16th IEEE International Conference on VLSI Design, January 4-8, 2003, New Delhi, India

Najeeb-ud-Din, V.Ramgopal Rao, and J.Vasi, “Small Signal Characteristics of Thin Film Single Halo SOI MOSFETs for Mixed Mode Applications”, Proceedings of the 16th IEEE International Conference on VLSI Design, January 4-8, 2003, New Delhi, India

Nihar. R. Mohapatra, S. Mahapatra, V. Ramgopal Rao, S. Shukuri and J. Bude, “Effect of Programming Biases on the Reliability of CHE and CHISEL Flash EEPROMs”, Proceedings of the International Reliability Physics Symposium (IRPS) 2003, March 30 - April 3, 2003, Dallas, Texas, USA

Nihar Mohapatra, Deleep Nair, Souvik Mahapatra, V. Ramgopal Rao, Shoji Shukuri, "The Impact of Channel Engineering on the Performance Reliability and Scaling of CHISEL NOR Flash EEPROMs", 33rd European Solid-State Device Research Conference (ESSDERC) 2003: 16 - 18 September 2003, pp. 541-544, Lisbon, Portugal

K.N.Manjularani, V.Ramgopal Rao, J.Vasi, "Relaibility of Ultrathin JVD Silicon Nitride MNSFETs under High Field Stressing" Proceedings of the 10 th IEEE International Symposium on Physical and Failure Analysis of Integrated Circuits, 7-11 July 2003, Singapore

Najeeb-ud-Din, V. Ramgopal Rao, and J. Vasi, "Thin Film Single Halo (SH) SOI nMOSFETs - Hot Carrier Reliability for Mixed Mode Applications" IEEE TENCON 2003, Convergent Technologies for the Asia-Pacific, October 14-17, 2003,Bangalore, India

K.N.Manjularani, V.Ramgopal Rao, J.Vasi, "Characterization of High-Field Stress-Induced Border Traps in JVD Si3N4 Transistors by Drain urrent Transient and 1/f Methods" 34th IEEE Semiconductor Interface Specialists Conference (SISC), December 4-6, 2003, Washington, D.C., USA

Najeeb-ud-Din, Aatish Kumar, Mohan V.Dunga, V.Ramgopal Rao, J.Vasi, “Suppression of Parasitic BJT Action in Single Pocket Thin Film Deep Sub-micron SOI MOSFETs”, Proceedings of the 2002 MRS Spring Meeting, San Francisco, California (April 1-5, 2002)

Nihar. R. Mohapatra, M. P. Desai, V. Ramgopal Rao, “Effect of Technology Scaling on MOS Transistors with High-K Gate Dielectrics”, Proceedings of the 2002 MRS Spring Meeting, San Francisco, California (April 1-5, 2002)

Krishna K. Bhuwalka, Nihar. R. Mohapatra, Siva G.Narendra, V. Ramgopal Rao, “Effective dielectric thickness Scaling for High-K Gate Dielectric MOSFETs”, Proceedings of the 2002 MRS Spring Meeting, San Francisco, California (April 1-5, 2002)

P.C.Waghmare, S.B.Patil, A.Kumbhar, R.O.Dusane, and V.Ramgopal Rao, “Improvement of Gate Dielectric Quality of MNS Capacitors by Hydrogen Etching for Ultra Thin Gate Dielectrics”, Proceedings of the 2002 MRS Spring Meeting, San Francisco, California (April 1-5, 2002)

K. N. ManjulaRani, V. Ramgopal Rao and J. Vasi, “Degradation Study of Ultra-Thin JVD Silicon Nitride MNSFET”, Proceedings of the 2002 MRS Spring Meeting, San Francisco, California (April 1-5, 2002)

Nihar. R. Mohapatra, Souvik Mahapatra and V. Ramgopal Rao, “Device Scaling Effects on Substrate Enhanced Degradation in MOS Transistors”, Proceedings of the 2002 MRS Spring Meeting, San Francisco, California (April 1-5, 2002)

A.Dixit, R.O.Dusane, and V.Ramgopal Rao, “Electrically Induced Junction MOSFET for High Performance Sub 50 nm CMOS Technology”, Proceedings of the 2002 MRS Spring Meeting, San Francisco, California (April 1-5, 2002)

Yatin Mutha, K.N.ManjulaRani, R.Lal and V.Ramgopal Rao, “Polarity Dependence of Degradation in Ultra Thin Oxide and JVD Nitride Gate Dielectrics”, Proceedings of the 2002 MRS Spring Meeting, San Francisco, California (April 1-5, 2002)

A.V. Vairagar, S.B. Patil, D.J. Pete, R.O. Dusane,, N. Venkatramani and V.Ramgopal Rao, “Suppression of Boron Penetration by Hot Wire CVD Polysilicon” Proceedings of the 9 th IEEE International Symposium on Physical and Failure Analysis of Integrated Circuits, 8-12 July 2002, Singapore

N.R Mohapatra, S. Mahapatra and V. Ramgopal Rao, “Bias and Time Dependene of Damage Generation in n-Channel MOS Transistors Operating in the Substrate Enhanced Gate Current Regime” Proceedings of the 9 th IEEE International Symposium on Physical and Failure Analysis of Integrated Circuits, 8-12 July 2002, Singapore

Yatin M. Mutha, R. Lal and V.Ramgopal Rao, “Physical Mechanisms for Pulsed AC Stress Degradation in Thin Gate Oxide MOSFETs” Proceedings of the 9 th IEEE International Symposium on Physical and Failure Analysis of Integrated Circuits, 8-12 July2002,Singapore.

Neeraj .K. Jha, M. Shojaei, V.Ramgopal Rao, “Performance and Reliability of Single Pocket Deep Submicron MOSFETs for Analog Applications”, Proceedings of the 9 th IEEE International Symposium on Physical and Failure Analysis of Integrated Circuits, 8-12 July 2002, Singapore

Neeraj K. Jha, V. Ramgopal Rao, and J.C.S.Woo, "Optimization of Single Halo p-MOSFET Implant Parameters for Improved Analog Performance and Reliability", Proceedings of the 32 nd European Solid-State Device Research Conference (ESSDERC), 24 - 26 September 2002, Florence, Italy

Parag C. Waghmare, Samadhan B. Patil, Alka A. Kumbhar, Laxmi Sahoo, V. Ramgopal Rao, and R.O. Dusane, “Nitrogen dilution effects on structural and electrical properties of hot wire deposited a-SiN:H films for Deep Sub-micron CMOS Technologies”, Proceedings of the International Conference on Cat-CVD (Hot-Wire CVD) Process, Denver, CO, USA, September 10-13, 2002

Samadhan B. Patil, Anand V. Vairagar, Alka A. Kumbhar, Laxmi K. Sahu, V. Ramgopal Rao, N. Venkatramani, R. O. Dusane and B. Schroeder, “Highly Conducting P+- PolySi Deposited by HWCVD and its Applicability As Gate Material for CMOS Devices” Proceedings of the International Conference on Cat-CVD (Hot-Wire CVD) Process, Denver, CO, USA, September 10-13, 2002

D. Vinay Kumar, R. A. Thakker, M. B. Patil, and V. Ramgopal Rao, "Simulation study of non quasi static behaviour of MOS transistors," Proc. 5th International Conference on Modeling and Simulation of Microsystems, San Juan, Puerto Rico, April 22, 2002

P.Poornima, S.K.Tripathy, V.Ramgopal Rao, and D.K.Sharma, “Resolution Enhancement Techniques for Optical Lithography”, Proceedings of the 11 th International Workshop on The Physics of Semiconductor Devices, December 11-15, 2001, Delhi, India (Invited)

Najeeb-ud-Din, V.Ramgopal Rao, and J.Vasi, “Characterization and simulation of Lateral Asymmetric Channel Silicon-on-Insulator MOSFETs”, Proceedings of the 11 th International Workshop on The Physics of Semiconductor Devices, December 11-15, 2001, Delhi, India

K.N.ManjulaRani, V.Ramgopal Rao, and J.Vasi, “High Field Stressing Effects in JVD Nitride Capacitors”, Proceedings of the 11 th International Workshop on The Physics of Semiconductor Devices, December 11-15, 2001, Delhi, India

A.Dixit, D.K.Pal, J.N.Roy, and V.Ramgopal Rao, “Channel Engineering for Sub-micron CMOS Technologies”, Proceedings of the 11 th International Workshop on The Physics of Semiconductor Devices, December 11-15, 2001, Delhi, India

D. Vinay Kumar, M. B. Patil, N. R. Mohapatra, V. Ramgopal Rao, B. Anand, and M. P. Desai, "A new look-up table circuit simulator," Proc. Chandigarh Symp. on Microelectronics, Punjab University, February, 2001 (Invited)

Mohan V. Dunga, Aatish Kumar, and V. Ramgopal Rao, “Analysis of Floating Body Effects in Thin Film SOI MOSFETs using the GIDL Current Technique”, Proceedings of 8 th IEEE International Symposium on Physical and Failure Analysis of Integrated Circuits, 9-13 July 2001, Singapore

Nihar. R. Mohapatra, M. P. Desai, Narendra Siva, V. Ramgopal Rao, “The Impact of High-K Gate Dielectrics on Sub 100nm CMOS Circuit Performance”, Proceedings of the 31 st European Solid-State Device Research Conference (ESSDERC), 11 - 13 September 2001, Nuremberg, Germany, September, 2001.

Nihar Mohapatra, Souvik Mahapatra, V.Ramgopal Rao, “"Study of Degradation in Channel Initiated Secondary Electron Injection Regime", Proceedings of the 31 st European Solid-State Device Research Conference (ESSDERC), 11 - 13 September 2001, Nuremberg, Germany, September, 2001.

Aatish Kumar, Rakesh Lal, and V. Ramgopal Rao, “A Simple and Direct Technique for Interface Characterization of SOI-MOSFETs and its Application in Sub 100nm JVD-MNSFETs”, 12 th Bi-annual conference on Insulating Films on Semiconductors, INFOS, June 20-23, 2001, Italy

Parag C.W, Samadhan Patil, Alka Kumbhar, R.O.Dusane, V.Ramgopal Rao, “Ultra thin Silicon Nitride by Hot Wire CVD for Deep Sub-Micron CMOS Technologies”, Proceedings of the Micro and Nanoengineering (MNE’01) Conference, September16-19, 2001,France

Najeebuddin, Aatish Kumar, Mohan V.Dunga, V.Ramgopal Rao, J.Vasi, “Characterization of Lateral Asymmetric Channel (LAC) Thin Film SOI MOSFETs”, 6 th International Conference on Solid-State and Integrated Circuit Technology (ICSICT), Shanghai, China, 22-25 th October, 2001 (Invited)

P.C.Waghmare, S.B.Patil, A.Kumbhar, R.O.Dusane, and V.Ramgopal Rao, “Reliability Issues of Ultra Thin Silicon Nitride by Hot-Wire CVD for Deep Sub-Micron CMOS Technologies”, Proceedings of the 11 th International Workshop on The Physics of Semiconductor Devices, December 11-15, 2001, Delhi, India

Mayank Gupta, V.Vidya, V.Ramgopal Rao, Kun H. To, Jason C.S. Woo, “Optimization of Sub 100 nm Gamma-Gate Si-MOSFETs for RF Applications” Proceedings of the 11 th International Workshop on The Physics of Semiconductor Devices, December 11-15, 2001, Delhi, India

Nihar. R. Mohapatra, Souvik Mahapatra and V. Ramgopal Rao, “A Comparative Study of Degradation for NMOSFET's in CHE and CHISEL Injection Regime”, Proceedings of the 11 th International Workshop on The Physics of Semiconductor Devices, December 11-15, 2001, Delhi, India

K.N. Manjularani, V.Ramgopal Rao, J.Vasi, “Border Trap Generation in JVD Nitride Capacitors Under High Field Stressing”, 31 st IEEE Semiconductor Interface Specialists Conference, November 28 - December 1, 2001, Washington D.C, USA

G. Shrivastav, S. Mahapatra, V. Ramgopal Rao, J. Vasi, K. G. Anil, C. Fink, W. Hansch and I. Eisele “Performance Optimization of 60 nm Channel Length Vertical MOSFETs Using Channel Engineering”, Proceedings of the 14th International Conference on VLSI Design, January 2001, Bangalore, INDIA

Nihar.R.Mohapatra, A.Dutta, M.P.Desai and V. Ramgopal Rao, “Effect of Fringing Capacitances in Sub 100 nm MOSFET's with High-K Gate Dielectrics” Proceedings of the 14th International Conference on VLSI Design, January 2001, Bangalore, INDIA

N.Mahapatra, M.P.Desai, and V.Ramgopal Rao, “Device and Circuit Performance Issues with High-K Gate Dielectrics”, Proceedings of the National seminar on VLSI: Systems, Design and Technology, IIT Bombay, Dec 2000.

Samadhan B.Patil, A.Kumbhar, P.Waghmare, V.Ramgopal Rao, and R.O.Dusane, “Low Temperatue Silicon Nitride deposited by Cat CVD for Deep Sub-micron CMOS Devices”, Proceedings of the International Conference on Cat-CVD (Hot-Wire CVD) Process, Kanazawa, Japan, November 2000

Nihar.R.Mohapatra, A.Dutta, G.Sridhar, M.P.Desai and V.Ramgopal Rao “Sub 100 nm CMOS Circuit Performance with High-K Gate Dielectrics” Proceedings of the 11th Workshop on Dielectrics in Microelectronics (WoDiM), November 13-15, 2000, Munich, Germany

Aatish Kumar, Souvik Mahapatra, Rakesh Lal, and V. Ramgopal Rao, “Multi-Frequency Transconductance Technique for Interface Characterization of Deep Sub-Micron SOI-MOSFETs”, Proceedings of the 11th Workshop on Dielectrics in Microelectronics (WoDiM), November 2000, Munich, Germany

K.G. Anil, S. Mahapatra, I. Eisele, V.Ramgopal Rao, and J. Vasi "Drain Bias Dependence of Gate Oxide Reliability in Conventional and Asymmetrical Channel MOSFETs in the Low Voltage Regime", Proceedings of the 30 th European Solid-State Device Research Conference (ESSDERC), Ireland, September, 2000

K.G. Anil, S. Mahapatra, V. Ramgopal Rao and I. Eisele, "Comparison of Sub-Bandgap Impact Ionization in Deep-Sub-Micron Conventional and Lateral Asymmetrical Channel nMOSFETs", Proceedings of the International Conference on Solid state Devices and Materials (SSDM) Sendai, Japan, August 28-31, 2000

S.Mahapatra, V.Ramgopal Rao, J.Vasi, B.Cheng, and J.C.S. Woo, "Reliability Studies on Sub 100 nm SOI-MNSFETs", Proceedings of the International Integrated Reliability Workshop, October 23-26, 2000, California, USA.

V. Ramgopal Rao, S. Mahapatra, J.Vasi, K. G. Anil, C. Fink, W. Hansch and I. Eisele, “Hot-Carrier Performance of 60 nm Channel Length Delta-Doped Vertical MOSFETs with High-pressure Grown Oxide as a Gate Dielectric”, Proceedings of the 30th IEEE Semiconductor Interface Specialists Conference, 2000, San Diego, California, USA

Samadhan B. Patil , Sangeeta Vaidya, Alka Kumbhar, R. O. Dusane, A. N. Chandorkar and V. Ramgopal Rao, “Low Temperature Hot-Wire CVD Nitrides for Deep Sub-Micron CMOS Technologies” Proceedings of the SPIE - The International Society for Optical Engineering, vol.3975, pt.1-2, (Tenth International Workshop on the Physics of Semiconductor Devices, New Delhi, India, 14-18 Dec.1999.) SPIE-Int. Soc. Opt. Eng, 2000. p.879-82

M. Hemkar, J.Vasi, V. Ramgopal Rao, B. Cheng, J.C.S. Woo, “Optimization and realization of sub 100 nm channel length lateral asymmetric channel p-MOSFETS” Proceedings of the SPIE - The International Society for Optical Engineering, vol.3975, pt.1-2, (Tenth International Workshop on the Physics of Semiconductor Devices, New Delhi, India, 14-18 Dec. 1999.) SPIE-Int. Soc. Opt. Eng, 2000. p.584-7.

Sharad Sharma, and V. Ramgopal Rao, “Performance Trade-offs by the Use of High-K Gate Dielectrics in Sub 100 nm CMOS Technologies”, Proceedings of the SPIE - The International Society for Optical Engineering, vol.3975, pt.1-2, (Tenth International Workshop on the Physics of Semiconductor Devices, New Delhi, India, 14-18 Dec. 1999.) SPIE-Int. Soc. Opt. Eng, 2000. p.896-9

Sushant S. Suryagandh, and V. Ramgopal Rao, “Dynamic Threshold Voltage MOSFETs for Future Low Power Sub 1V CMOS Applications”, Proceedings of the SPIE - The International Society for Optical Engineering, vol.3975, pt.1-2, (Tenth International Workshop on the Physics of Semiconductor Devices, New Delhi, India, 14-18 Dec. 1999.) SPIE-Int. Soc. Opt. Eng, 2000. p.655-8

S. Mahapatra, K. N. Manjularani, V. Ramgopal Rao, J. Vasi, " ULSI MOS Transistors with Jet Vapour Deposited (JVD) Silicon Nitride for the Gate Insulator", Proceedings of the SPIE - The International Society for Optical Engineering, vol.3975, pt.1-2, (Tenth International Workshop on the Physics of Semiconductor Devices, New Delhi, India, 14-18 Dec. 1999.) SPIE-Int. Soc. Opt. Eng, 2000. p.803-10

S. Mahapatra, V. Ramgopal Rao, C. D. Parikh, J. Vasi, B. Cheng and J. C. S.Woo, "Hot-Carrier Induced interface Trap Distributions in Conventional and Asymmetric Channel MOSFETs as Determined by a novel Charge Pumping Technique" Presented at the 30 th Semiconductor Interface Specialists Conference (SISC), South Carolina, USA, December 1999

S. Mahapatra, V. Ramgopal .Rao, C.D.Parikh, J.Vasi, B.Cheng, and J.C.S.Woo, "A Study of 100 nm Channel Length Asymmetric MOSFETs by Using Charge Pumping", Proceedings of the Insulating Films on Semiconductors (INFOS), June 1999, Kloster Banz,Germany.

S.Mahapatra, V.Ramgopal Rao, K.N. Manjularani, C.D. Parikh, J. Vasi, B. Cheng, M. Khare, and J.C.S. Woo, "100 nm Channel Length MNSFETs using a Jet Vapor Deposited Ultra-thin Silicon Nitride Gate Dielectric", Technical Digest, 1999 Symposium on VLSI Technology, June 14-19, Kyoto, Japan

B.Cheng, A.Inani, V.Ramgopal Rao, and J.C.S.Woo, "Channel Engineering for High Speed Sub-1.0 V Power Supply Deep Sub-Micron CMOS" Technical Digest, 1999 Symposium on VLSI Technology, June 14-19, Kyoto, Japan

S. Mahapatra, V. Ramgopal Rao, C. D. Parikh, J. Vasi, B. Cheng, M. Khare and J. C. S. Woo , "Hot-Carrier Induced Interface Degradation in Jet Vapor Deposited SiN MNSFETs as Studied by a Novel Charge Pumping Technique" p. 592-595, 29 th European Solid-State Device Research Conference (ESSDERC), Leuven, Belgium 13 - 15September,1999.

A. Inani, V. Ramgopal Rao, B. Cheng, P. Zeitzoff, and J. C. S. Woo, “Capacitance Degradation due to Fringing Fields in Deep Sub-Micron MOSFETs with High-K Gate Dielectrics” p.160-163, 29 th European Solid-State Device Research Conference (ESSDERC), Leuven, Belgium 13 - 15 September, 1999

V. Ramgopal Rao, W.Hansch, S.Mahaptra, D.K.Sharma, J.Vasi, T.Grabolla, and I.Eisele, “Low Temperature-High Pressure Grown Thin Gate Dielectrics for MOS Applications”, Proceedings of the Insulating Films on Semiconductors (INFOS), June 1999, Kloster Banz,Germany

V. Ramgopal Rao, G. Wijeratne, D. Chu, T. Brozek, and C.R. Viswanathan, “Plasma Process Induced Abnormal 1/f Noise Behavior in Deep Sub-Micron MOSFETs”, 3 rd International Symposium on Plasma Process-Induced Damage (P2ID), Hawaii, USA, June,1998

W.Hansch, A.Nakajima, K.Shibahara, V. Ramgopal Rao and I.Eisele, “Observation of Periodic Current Oscillations in Vertical sub-100nm MOS-PDBFETs with Wide Channels”, 1998 IEEE Silicon Nanoelectronics workshop, (Satellite Workshop, VLSI T.echnology Symposium) Honolulu, Hawaii, USA, June, 1998

C.R. Viswanathan and V. Ramgopal Rao, "Application of charge pumping technique for sub-micron MOSFET characterization" Presented at the Electrical and Physical Characterization of Materials and Devices for Silicon Microelectronics. MIGAS, Autrans, France, 29 June -5 July 1998

A.Inani, B.Cheng, V. Ramgopal Rao, and J.C.S.Woo, “Gate Stack Architecture Analysis in sub 100 nm Channel Length MOSFETs” , 5 th National SRC Conference TECHCON, 1998, Las Vegas, USA

B.Cheng, V. Ramgopal Rao, B.Ikegami, and J.C.S.Woo, “Realization of sub 100 nm asymmetric Channel MOSFETs with Excellent Short-Channel Performance and Reliability” Technical Digest, 28 th European Solid-State Device Research Conference (ESSDERC), Bordeaux, France, 1998

R.Sachdev, G.Wijeratne, V. Ramgopal Rao, and C.R.Viswanathan, “A study of the effect of Plasma Damage on Sub-micron MOSFET’s Flicker Noise Properties”, Technical Digest, 28th European Solid-State Device Research Conference (ESSDERC), Bordeaux, France,1998.

A.Inani, V.Ramgopal Rao, B.Cheng, M.Cao, P.V.Voorde, W.Greene, and J.C.S. Woo, “Performance Considerations in Using High-k Dielectrics for Deep Sub-Micron MOSFETs”, Proceedings of the Solid state Devices and Materials (SSDM) Research Conference, Hiroshima, Japan, 7-10 Sept., 1998

B. Cheng, V. Ramgopal Rao, and J. C. S. Woo, “Sub 0.18 um SOI MOSFETs Using Lateral Asymmetric Channel Profile and Ge Pre-amorphization Salicide Technology”, Proceedings of the IEEE SOI Conference, October 5-8, Stuart, Florida, USA, 1998

W. Hansch, V.Ramgopal Rao, and I.Eisele, "The Planar-Doped-Barrier FET:MOSFET Overcomes Conventional Limitations", Technical Digest, p. 624, 27 th European Solid-State Device Research Conference (ESSDERC), Stuttgart, Germany, September, 1997

W. Hansch, F. Kaesen, V.Ramgopal Rao, and I. Eisele, “Electric field-tailoring in MBE-grown MOSFETs”, Technical Digest, p. 117, 7th International Symposium on Silicon Molecular Beam Epitaxy, Banff, Canada, July 1997

V. Ramgopal Rao, W. Hansch, and I. Eisele, "Simulation, Fabrication and Characterization of High Performance Planar-Doped-Barrier Sub 100 nm Channel MOSFETs" Technical Digest, IEEE International Electron Devices Meeting (IEDM), p. 811-814, Washington DC, USA, December, 1997

Anand Sridharan, V.Ramgopal Rao, Tomasz Brozek, J. Werking, and C.R.Viswanathan, "Charge Injection using Gate-Induced-Drain-Leakage Current for Characterization of Plasma Edge Damage in CMOS Devices", Technical Digest, p. 560, 27 th European Solid-State Device Research Conference (ESSDERC), Stuttgart, Germany, September, 1997

C.R.Viswanathan, V.Ramgopal Rao and T.Brozek, "Localized Charge Injection-A Tool to Investigate Plasma Damage in CMOS Devices" (invited) Proceedings of the 9 th International Conference on Physics of Semiconductor Devices, December, 1997, New Delhi, India

V.Ramgopal Rao, W.Hansch, H.Baumgartner, I.Eisele, D.K.Sharma, J.Vasi, and T.Grabolla, “Charge Trapping Behavior in Deposited and Grown Thin MOS Gate Dielectrics”, Proceedings of the European Materials Research Society (EMRS) Symposium, 1996 Spring Meeting, Strasbourg, France

V. Ramgopal Rao, I. Eisele, and T. Grabolla, "Alternative Gate Insulators for Future Deep Submicron Channel Length MOSFETs", Proc. of VIII International Conference on Physics of Semiconductor Devices, December, 1995, New Delhi, India

A. Mallik, V. Ramgopal Rao, A.N. Chandorkar, and J. Vasi, "Trap generation upon irradiation in reoxidised nitrided oxide gate dielectrics", Proc. of VII International conference on Physics of Semiconductor Devices, December, 1993 New Delhi, India

NATIONAL CONFERENCE PROCEEDINGS:

Manoj Joshi, Nitin Kale, Sheetal Patil, Harshal Rokade, Soumyo Mukherji, R.Pinto, .P.R.Apte, Rakesh Lal and V.Ramgopal Rao, "Affinity Cantilever sensors for Myocardial Infarction",International Microelectronics and Packaging Society (IMAPS) India National Conference, Dec 20-21, 2005, Mumbai

M. V. Rammohan Reddy, D. Vinay Kumar, D. K. Sharma, M. B. Patil and V. Ramgopal Rao, "FinFET based Low Power Gilbert Cell Mixer", International Microelectronics and Packaging Society (IMAPS) India National Conference, Dec 20-21, 2005, Mumbai

Seena V., Mahendra K. Jain, V. Ramgopal Rao,S.Praveenkumar, Anita Topkar, "ONO based Triple dielectric passive dosimeters", DAE-BARC National Symposium on Compact Nuclear instruments and Radiation Detectors, March 2-4, 2005, Jodhpur, India

V.Ramgopal Rao, K.Narasimhulu, "CMOS Device Design and Optimization for System-on-Chip Applications", Emerging Trends in Electronics (Electro -2005), February, 03-05, 2005, Banaras Hindu University, Varanasi (Invited)

V.Ramgopal Rao, K.Narasimhulu,"Novel Device Architectures and Processes for the 65 nm CMOS Technology Node and Beyond", Indian National Academy of Engineering (INAE) Conference on Nanotechnology (ICON-2003), Dec. 22-23, 2003, Chandigarh, India (Invited)

BOOK CHAPTERS:

"Rare earth oxides in microelectronics", Kuniyuki Kakushima, Kazuo Tsutsui, Sun-ichiro Ohmi, V. Ramgopal Rao, and Hiroshi Iwai; RARE EARTH OXIDE THIN FILMS: Growth,Characterization, and Applications,Springer-Verlag Series on “Topics in Applied Physics”, Edited by M. Fanciulli and G. Scarel, Ed. 2005

"Polymers in Electronics", Saurabh Goyal, V.Ramgopal Rao; SPECIALITY POLYMERS, I.K. International Private Limited, New Delhi(India), Edited by Dr. Faiz Mohammad, Ed. 2005

(SELECTED)TECHNICAL REPORTS:

Vijay Mishra, Pourus Mehta, S. K. Kataria and V. Ramgopal Rao, "Development of Silicon Drift Detectors with Integrated Front End Electronics", Design Basis Report, BARC, Mumbai, 2004

V.Ramgopal Rao, "Channel engineering for Sub 100 nm MOSFETs", Department of Science and Technology, Govt. of India, 2003

C.R.Viswanathan and V. Ramgopal Rao, “Plasma Damage Studies Using SPIDER Structures”, Microelectronic Innovation and Computer Research Opportunities (MICRO), University of California, 1998

V. Ramgopal Rao "Radiation Induced Interface State Generation in Nitrided and Reoxidized Nitrided Gate Oxides" Department of Electronics, MHRD, Govt. of India 1992

PATENTS:

Manoj Joshi, Nitin Kale, S.Mukherji, R.O.Dusane, V. Ramgopal Rao, Rakesh Lal, “A novel dry method or surface modification of SU8 for immobilisation of biomolecules using hotwire induced pyrolytic process”, Patent pending, 2004

H. Gossner, F. Wittmann, I. Eisele, and V.Ramgopal Rao, “SRAM Memory Cell”, United States Patent No. 6,067247, May 23, 2000

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