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Workshop Program (pdf)
Jan 7 (Thursday)
Venue: Faculty
Hall, IISc
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5:00 pm - 5:45 pm
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Registration and
Reception
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5:45 pm - 6:00 pm
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Inaugural ceremony
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6:00 pm - 6:45 pm
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Keynote address
Speaker:
Yervant Zorian, Virage Logic, USA
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6:45 pm - 7:30 pm
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Banquet Speech
Speaker: Greg
Taylor, Intel, USA
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7:45 pm - 8:15 pm
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Cultural
Program
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8:30 pm - 9:30 pm
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Dinner
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Jan 8 (Friday)
Venue: Faculty
Hall, IISc
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9:00 am - 9:45 am
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Embedded
Tutorial
Speaker:
Abhijit Chatterjee, Georgia Tech, USA
Topic: Adaptive Signal Processing: Handling Variability and
Workload in Communications Systems
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9:45 am - 10:15 am
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Invited Talk -
II
Speaker: Mark
Zwolinski, Southampton Univ., UK
Topic: Modelling Variability in Nano-Scale CMOS for Reliable Design
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10:15 am - 10:45 am
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Coffee Break
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10:45 am - 11:15 am
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Invited
Talk - III
Speaker:
Bernd Becker, Univ. of Freiburg, Germany
Topic: On Verification,
Test and Reliability of Complex Systems
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11:15 am - 12:35 pm
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Session
- 1: Modelling for Reliability
Chair:
Michiko Inoue, NAIST, Japan
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1.1
A Path Selection Method for Delay Test
Targeting Transistor Aging
Mitsumasa Noda, Seiji
Kajihara, Yasuo Sato, Kohei Miyase, Xiaoqing Wen and Yukiya Miura
Kyushu Institute of
Technology, Japan
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1.2
Modeling and Reliability Evaluation of logic
Circuits at Nanoscale
Renu Kumawat, Vineet
Sahula, M. S. Gaur and Vijay Laxmi
Malaviya National Institute
of Technology, Jaipur, India
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1.3
A Yield Model of Design for Testability
and Repairability
Hideyuki Ichihara, Yujiro Amano,
Yuki Yoshikawa and Tomoo Inoue
Hiroshima City University,
Japan
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1.4
Equation-Based Vdd-Aware Model for
Resistive Bridge Behavior
Urban Ingelsson
Linkoping University,
Sweden
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12:35 pm - 2:00 pm
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Lunch Break
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2:00 pm - 2:30 pm
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Invited
Talk - IV
Speaker:
M. Ravindra, Indian Space Research Organization, India
Topic: Challenges for
space qualified electronic systems
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2:30 pm -3:50 pm
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Session
-2: Advances in Test
Chair:
Seiji Kajihara, Kyushu Institute of Technology, Japan
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2.1 Optimizing
Delay Test Quality with a Limited Number of Test Set
Michiko Inoue, Akira
Taketani, Tomokazu Yoneda, Hiroshi Iwata and Hideo Fujiwara
Nara Institute of Science
and Technology, Japan
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2.2 Run Length
Based Test Data Compression Techniques: How Far From Entropy and Power
Bounds?
Usha Mehta, Kankar Dasgupta
and Niranjan Devashrayee
Nirma University,
Ahmedabad, and ISAC, Ahmedabad
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2.3 Development
of Automatic Program Generation Tool for Analog-Mixed Signal and RF Load
Boards
Sukeshwar Kannan, Bruce
Kim, Ganesh Srinivasan, Friedrich Taenzlar, Richard Antley, Chris Vogel and
Craig Force
Univ. of Alabama, USA, and
Texas Instruments, Dallas, USA
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2.4 A
System Maintenance Architecture via Ethernet
Hyunbean Yi and Sandip
Kundu
University of
Massachussets, USA
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3:50 pm - 4:10 pm
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Coffee Break
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4:10 pm - 5:30 pm
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Session
- 3: System Level Reliability
Chair:
Hideyuki Ichihara, Hiroshima City University, Japan
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3.1 Lifetime
Reliability Optimization for Embedded Systems: A System-Level Approach
Michael Glass, Martin
Lukasiewycz, Christian Haubelt and Jurgen Teich
University of
Erlangen-Nuremberg, Germany
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3.2 On-line
techniques to adjust and optimize checkpointing frequency
Dimitar Nikolov, Urban
Ingelsson, Virendra Singh and Erik Larsson
Linkoping Univ., Sweden,
and IISc, Bangalore, India
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3.3 Minimal
path, Fault Tolerant, QoS aware Routing in 2-D Mesh NoC
Navaneeth R., M. Ahmed,
M.S. Gaur, V. Laxmi and K.K. Paliwal
Malaviya National Institute
of Technology, Jaipur, India
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3.4 Adaptive
Voltage Over-Scaling for Resilient Applications
Philipp Klaus Krause and
Ilia Polian
University of Freiburg,
Germany
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5:30 pm - 6:00 pm
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Invited
Talk - V
Speaker:
Shubu Mukherjee, Intel, USA
Topic: Architecting a
reliable system
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6:00 pm -6:15 pm
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Coffee Break
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6:15 pm -7:15 pm
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Panel
Discussion
Topic:
End of CMOS Roadmap - Reliability and Test Challenges
Moderator:
Ilia Polian, Freiburg Univ., Germany
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Panelists:
Sandeep Kundu, Univ. of
massachussets, USA
Shubu Mukherjee, Intel,
USA
Souvik Mahapatra, IIT
Mumbai, India
Mehdi Tahoori,
Northeastern Univ., USA
Michael Glass, Univ. of
Erlangen-Nuremberg
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7:15 pm - 7:30 pm
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Closing
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7:30 pm - 8:30 pm
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Dinner
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Note for VLSI Design Conference attendees: Two buses are arranged
for VLSI Design conference attendees to travel to IISc (at 4:15 pm and 4:25
pm) on Jan 7, 2010.
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