Advance Program (PDF)

Day-1: 6^th January (Thursday)

Venue: IIT Madras, Chennai

Time	Program
9:00 am - 2:00 pm	Registration
2:00 pm - 2:15 pm	Inaugural Ceremony
2:15 pm - 3:00 pm	Keynote Address Speaker: John Carulli, Texas Instruments, USA
3:00 pm - 3:45 pm	Embedded Tutorial Speaker: Masahiro Fujita, Tokyo University, Japan Topic: Post Silicon Debug
3:45 pm - 4:15 pm	Coffee Break
4:15 pm - 4:45 pm	Invited talk - I Speaker: Arun Somani, Iowa State University, USA Topic: RAKSHA: Reliable and Aggressive frameworK for System design using High-integrity Approaches
4:45 pm - 5:45 pm	Session - I Topic: Power Aware Design and Test Session Chair: Seiji Kajihara, Kyushu Institute of Technology, Japan
5:45 pm - 6:15 pm	Invited Talk - II Speaker: Sanjit Seshia, Univ. of California, Berkeley, USA Topic: On Voting Machine Design for Verification and Testability
6:30 pm - 8:30 pm	Cultural program and Banquet

Day-2: 7^th January (Friday)

Venue: IIT Madras, Chennai

Time	Program
8:30 am - 9:15 am	Keynote - II Speaker: Michel Renovell, LIRMM, France
9:15 am - 10:45 am	Special Session on Hardware Security Session Chair: Ilia Polian, Univ. of Passau, Germany Speakers Jacob Abraham, Univ. of Texas, Austin Michiko Inoue, NAIST, Japan Rajat Moona, IIT Kanpur, India
10:45 am - 11:15 am	Coffee Break and Poster
11:15am - 12:15 am	Session - II Topic: VLSI Test Session Chair: Mark Zwolinski, Southampton Univ., UK
12:15 am -12:45 pm	Invited Talk - III Speaker: M. Ravindra, ISRO, India Topic: Reliability and Quality Assurance of Application Specific Integrated Circuits for Space Applications
12:45 pm - 1:45 pm	Lunch Break
1:45 pm -3:15 pm	Session - III Topic: Reliable Systems Session Chair: Tomokazu Yoneda, NAIST, Japan
3:15 pm - 3:45 pm	Coffee Break
3:45 pm -5:15 pm	Panel Discussion Topic: Volume Diagnosis: Power in Numbers? Moderator: Sudhakar Reddy, Iowa University, USA
	Panelists: Srikant Venkataraman, Intel, USA Nagesh Tamrapalli, AMD, India Rubin Parekhji, Texas Instruments, India Adit Singh, Auburn University, USA Vishwani Agrawal, Auburn University, USA
5:15 pm - 5:30 pm	Closing

Session-I: Power Aware Design and Test

S1.1. A Test Pattern Optimization to Reduce Spatial and Temporal Temperature Variations

Tomokazu Yoneda, Makoto Nakao, Michiko Inoue, Yasuo Sato, and Hideo Fujiwara

(NAIST, Japan, and Kyushu Institute of Technology, Japan)

S1.2. Test Scheduling for 3D Stacked ICs Under Power Constraints

Breeta SenGupta, Urban Ingelsson, and Erik Larsson

(Linkoping University, Sweden)

S1.3. Low Power Programmable Controllers for Reliable and Flexible Computing

Masahiro Fujita, Hiroaki Yoshida, and Jaeho Lee

(Tokyo University, Japan)

Session-II: VLSI Test

S2.1. Dynamic Scan Clock Control in BIST Circuits

Priadarshini Shanmugasundaram and Vishwani Agrawal

(Auburn University, USA)

S2.2. A Pattern Partitioning Algorithm for Field Test

Senling Wang, Seiji Kajihara, Yasuo Sato, Xiaoxin Fan, and Sudhakar Reddy

(Kyushu Institute of Technology, Japan, and University of Iowa, USA)

S2.3. Optimal Universal Test Set for Bridging Faults Detection in Reversible Circuit Using Unitary Matrix

Susanta Chakraborty, Pradyut Sarkar, and Bikramadittya Mondal

(BESU Sibpur, Simplex Infrastructure, and BPPIMT, Kolkata)

Session-III: Reliable Systems

S3.1. On The Design of Self-Recovering Systems

Yang Lin and Mark Zwolinski

(Southampton University, UK)

S3. 2. Approximate and Bottleneck High Performance Routing for Self-healing VLSI Circuits

Achira Pal, Tarak Mandal, Alak Datta, Rajat Pal, Atal Chaudhuri

(HSBS, PMI Service Centre Europe Krakow Poland, Asam Univesrity Silchar, and Jadavpur University Kolkata)

S3.3. A Scalable Heuristic for Incremental High-Level Synthesis and Its Application to Reliable Computing

Shohei Ono, Hiroaki Yoshida, and Masahiro Fujita

(Tokyo University, Japan)

S3.4. A Study of Failure Mechanisms in CMOS & BJT ICs and Their Effect on Device Reliability

Adithya Thaduri, M. Rajesh Gopalan, Gopika Vinod, and Ajit Verma

(IIT Bombay, BARC, and IIIT Pune)

Posters

P1. Test Data Compression Technique for IP Core Based SoC using Artificial Intelligence

Usha Mehta, KS Dasgupta, Nirjan Devashrayee, and Harikrishna Parmar

(Nirma University Ahmedabad and ISAC Ahmedabad)

P2. A Design Methodology for Specification and Performances Evaluation of Network-on-Chip

Adrouche Djamel, Sadoun Rabah, and Pillement Sebastien

(Ecole Nationale Politechnique Algeria, and Univ. of Rennes)

P3. FOCAS: A Novel Framework for System-On-Chip Datapath Validation

Balvinder Khurana, and Atul Gupta

(Freescale Semiconductors, Noida, India)

P4. Synthesis of Reversible Logic Circuit using Unitary Matrix

Susanta Chakraborty, Bikramadittya Mondal and Pradyut sarkar

(BESU Sibpur, BPPIMT Kolkata, and Simplex Infrastructure Kolkata)

P5. Efficient SOPC-Based Multicore System Design Using NOC

Arunraj Subramanyan, Vanchinathan Thankavel

(Anna University and Femto Logic Design)