4^th IEEE International Workshop on Reliability Aware System Design and Test

(In conjunction with the International Conference on VLSI Design)

Pune, India January 9-10, 2013

Technical Program

Day 1 (Jan 9)

5:30 pm -- 5:40 pm	Inauguration and Opening Remarks
5:40 pm -- 6:20 pm	Keynote 1 Speaker: Prof. Raimund Ubar
6:20 pm -- 7:00 pm	Invited Talk 1 Speaker: Prof. Seiji Kajihara

Day 2 (Jan 10)

9:00 am -- 9:40 am	Keynote 2 Speaker: Prof. Jacob Abraham
9:40 am -- 10:15 am	Invited Talk 2 Speaker: Prof. Masahiro Fujita
10:15 am -- 11:45 am	Coffee Break
11:45 am -- 12:45 pm	Session 1 Fault tolerance Session Chair: Prof. Raimund Ubar
12:45 pm -- 1:45 pm	Lunch Break
1:45 pm -- 2:30 pm	Embedded Tutorial Speaker: Prof. Adit Singh
2:15 pm – 3:15 pm	Session 2 Reliability of Issues Session Chair: Prof. Kewal Saluja
3:15 pm -- 3:45 pm	Coffee Break
3:45 pm -- 4:45 pm	Session 3 Reconfigurable Design Session Chair: Prof. M.S. Gaur
4:45 pm -- 5:00 pm	Closing

Session 1: (Fault Tolerance)

S1.1 Fault tolerant XY routing in NoC using LBDR

Rimpy, Manoj Kumar, Vijay Laxmi, and M.S. Gaur (MNIT, Jaipur)

S1.2 An availability model for planning self test and repair processes for fault

tolerant FPGA-based systems

Shampa Chakravarty, Anubhav Agrawal, Broteen Kundu (NSIT, Delhi)

S1.3 A design for testability technique of reversible circuits using duplication techniques

Joytee Mondal, Debesh K Das (Jadavpur Univ.), Deepak Kole, and Hafizur Rahman (BESU, Kolkata)

Session 2: (Reliability of Issues)

S2.1 A weakely fault tolerant design of molecular memory cell

Renu Kumawat, Vineet Sahula, and M.S. Gaur (MNIT, Jaipur)

S2.2 CNT Interconnect Performance Optimization and

Comparison with Copper at 22nm Technology

Kureshi A.K (Vishwabharati college of Engg, Ahmed Nagar), Mohd. Hasan (AMU, Aligarh)

S2.3: Timing driven variation aware uniform geometry Steiner tree construction

Radhamanjari Samanta, Somyendu Raha (IISc, Bangalore), Edil Erzin (Russian Academiy of Sciences, Novosibirsk)

Session 3: (Reconfigurabel design)

S3.1 A Novel Application-aware Parallel and Reconfigurable fault-tolerant self-healing System

Deepa Jose, Nirmal Kumar, Jaykumar P (College of Engineering, Guindy)

S3.2 Design of self-reconfigurable adder for fault tolerant VLSI architectures

Atin Mukherjee and A.S. Dhar (IIT Kharagpur)

S3.3 Low activity scan FF design for power aware test

Ashok Suhag (GB Univ., Noida) , Satdev Ahlawat (KU, Kurukshetra), Jaynarayan (IISc, Bangalore)

S3.4 Peak power estimation for power grid design (Invited paper)

Jaynarayan Tudu (IISc, Bangalore), Deepak Malani, and Virendra Singh (IIT Bombay)