5th IEEE International Workshop on
Reliability Aware System Design and Test (In
conjunction with the International Conference on VLSI Design) IIT Bombay, Mumbai, India, January 9-10,
2014 |
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Organizing
Committee General Co-Chairs Adit Singh (Auburn U., US) Virendra Singh (IIT-B, IN) General Vice Co-Chairs Michiko Inoue (NAIST, JP) Sreejit Chakravarty (LSI, US) Program Co-Chairs Erik Larsson (Lund U. SE) Rubin Parekhji (TI, IN) Program Vice Co-Chairs Ilia Polian (Passau U., DE) MS Gaur (MNIT, IN) Organizing Committee
Co-Chairs Bhargab Bhattacharya (ISI, IN) V. Kamakoti (IITM, IN) Publication Chair Vijay Laxmi (MNIT, IN) Finance Co-Chair Pradip Thaker (Maxim, IN) S. Ramakrishnan (WT, IN) Publicity Chair: Susanta Chakravarty (BESU, IN) Chia Yee Ooi (TUM, MY) Local Arrangement chair TBD Website management chair Sushil Kabra (BSNL, IN) Registration Chair Jaynarayan Tudu (IISc, IN) Deepak Malani (IIT-B, IN) Steering Committee: K.K. Saluja (US)
– Chair J.A. Abraham (US) V.D. Agrawal (US) B. Al-Hashimi (UK) B. Becker (DE) A. Chatterjee (US) H. Fujiwara (JP) M. Fujita (JP) E. Larsson (SE) R. Parekhji (IN) S.M. Reddy (US) A.D. Singh (US) V. Singh (IN) Program Committee: TBD
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Submission deadline is
extended to October 31, 2013 Even as advances in CMOS technology come up
against physical limits of material properties and lithography, raising many
new challenges that must be overcome to ensure IC quality and reliability,
there appears to be no obvious alternate technology that can replace
End-of-Roadmap CMOS over the next decade. However, many reliability
challenges from increasing defect rates, manufacturing variations, soft
errors, wearout, etc. will need to be addressed by innovative new design and
test methodologies if device scaling is to continue on track as per Moore`s
Law to 10nm and beyond. The
key objective of this annual workshop, planned to be held
in conjunction with the International Conference on VLSI Design, is to
provide an informal forum for vigorous creative discussion and debate of this
area. The aim is to encourage the presentation and discussion of truly
innovative and `out-of-the-box` ideas that may not yet have been fully
developed for presentation at reviewed conferences to address these
challenges. Additionally, the
workshop invites embedded talks and tutorials on cutting edge topics related
to reliability aware design of CMOS and hybrid nanotechnology systems. Representative
topics include, but are not limited to:
Submissions Authors are invited to submit previously unpublished
technical proposals. The proposals must be full papers not to exceed 6 pages.
Each submission should include: title, full name and affiliation of all
authors, a short abstract of 50 words, and 6 to 7 keywords. Also,
identify a contact author and include a complete correspondence address,
phone number, fax number, and e-mail address. Submit a copy of your proposal
in PDF either online submission via workshop website http://www.ee.iitb.ac.in/~rasdat/rasdat14
or to rasdat@ee.iitb.ac.in Submissions are due no later than October 31, 2013 (Extended). Authors will be notified of the disposition of
their presentation by November 10, 2013. Authors of accepted
presentations must submit the final paper by December 1, 2013 for
inclusion in the Workshop Proceedings, which will be provided to the
attendees. General Information
Program Related Information
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