Design Feature: March 3, 1994
Consider a typical convergence problem. Spice makes an initial guess at a circuit's node voltages and, using the circuit conductances, finds the mesh currents. It then uses the currents to recalculate the node voltages and starts the cycle again. The procedure continues until all of the node voltages settle to within certain tolerance limits, which you can alter with .OPTIONS parameters, such as RELTOL, VNTOL, and ABSTOL.
However, if the node voltages do not settle down within a certain number of iterations, then the dc analysis results in an error message, such as "No convergence in dc analysis," "PIVTOL Error," "Singular Matrix," or "Gmin/Source Stepping Failed." Spice then terminates the run because both the ac and transient analyses require an initial stable operating point to start.
During the transient analysis, the iterative process repeats for each individual time step. If the node voltages do not settle down, Spice reduces the time step and tries again to determine the node voltages. But, if the time step reduces beyond a certain fraction of the total analysis time, the transient analysis issues an error message ("Time step too small"), and the analysis halts.
Solutions to the dc analysis may fail to converge because of incorrect initial voltage guesses, model discontinuities, unstable/bistable operating points, or unrealistic circuit impedances. Model discontinuities or unrealistic circuit, source, or parasitic modeling are usually the causes of transient-analysis failure. The various solutions to convergence problems fall under one of two types. Some are simply Band-Aids: They merely try to fix the symptom by adjusting the simulator options. Other solutions actually effect the real cause of the convergence problems.
The following techniques provide solutions for 90 to 95% of all convergence problems. They're applicable to most Spice programs, especially those that are compatible with Berkeley Spice. They cover dc convergence, dc sweep convergence, and transient convergence with numbered solutions, beginning with 0, in each category. When you encounter a convergence problem, start at solution 0, and continue with subsequent solutions until convergence occurs.
The numerical order of the solutions is such that you can leave lower numbered fixes in your simulation as you add more fixes. The lower numbered fixes are also the most beneficial. Note, though, that fixes involving simulation options may simply mask underlying circuit instabilities. Invariably, you will find that once you've properly modeled your circuit, you no longer require many of the "options" fixes.
The following solutions apply to problems with dc convergence:
Solution 0. Check the circuit topology and connectivity. .OPTIONS NODE LIST provides a summary printout of nodal connections. To avoid common mistakes, make sure that:
Solution 1. Increase ITL1 to 300 in the .OPTIONS statement. For example, ".OPTIONS ITL1=300'' increases the number of dc iterations that Intusoft's Spice goes through before giving up.
Solution 2. Set ITL6=100 in the .OPTIONS statement. For example, ".OPTIONS ITL6=100'' invokes the source-stepping algorithm and uses 100 steps. (This solution is unnecessary for IsSpice3 users. IsSpice3 automatically invokes source stepping after trying both the default method and the new Gmin stepping algorithms.) This is an undocumented option in Spice 2 programs.
Solution 3. Add .NODESETs. For example, specify ".NODESET V(6)=0." Check the node-voltage table in the output file. Add .NODESETS statements to nodes that IsSpice says have unrealistic or unlikely voltages. Use a .NODESET of 0V if you do not have a better estimation of the proper dc voltage.
Solution 4. Add resistors and use OFF keyword. For example, specify "D1 1 2 DMOD OFF" and "RD1 1 2 100MEG." Add resistors across diodes to simulate leakage. Add resistors across MOSFET drain-to-source connections to simulate realistic channel impedances. Add ohmic resistances (RC, RB, RE) to transistors. Reduce Gmin an order of magnitude in the .OPTIONS statement. Add the OFF keyword to semiconductors (especially diodes) that may be causing convergence problems. The OFF keyword tells IsSpice to first solve the operating point with the device off. Then, the device turns on, and the previously found operating point is at a starting condition for the final operating point.
Solution 5. Change dc power supplies into PULSE statements. For example, changing "VCC 1 0 15 DC" to "VCC 1 0 PULSE 0 15'' lets you selectively turn on certain power supplies, just like in real life. This approach is sometimes called the "pseudo-transient" method. Use a reasonable rise time in the PULSE statement to simulate realistic turn-on. For example, "V1 1 0 PULSE 0 5 0 1U" provides a 5V supply with a turn-on time of 1 msec. The first value after the voltage value of 5 (in this case, 0) is the turn-on delay that you can use to let the circuit settle down before turning on the power supply.
Solution 6. Use initial conditions by inserting a UIC keyword in the TRAN statement. For example, specifying ".TRAN .1N 100N UIC" causes IsSpice to completely bypass the dc analysis. Add any applicable ".IC" and "IC=" initial-condition statements to assist in the initial stages of the transient analysis. This solution is not viable for performing an ac analysis because an operating point must precede the ac analysis.
Use solutions 5 and 6 only as a last resort because they do not produce a valid dc operating point for the circuit (all supplies turned on). However, solutions 5 and 6 can help you get to the transient analysis, where you may uncover hidden problems plaguing the dc analysis.
The following solutions apply to problems with dc sweep convergence:
Solution 0. Check circuit topology and connectivity (as in solution 0 in the dc analysis).
Solution 1. Set ITL2=100 in the .OPTIONS statement. For example, ".OPTIONS ITL2=100" increases the number of dc iterations IsSpice goes through before giving up.
Solution 2. Make the steps in the .DC sweep larger or smaller. For example, change ".DC VCC 0 1 .1'' to ".DC VCC 0 1 .01." Discontinuities in the Spice models can cause convergence problems. Larger steps can help bypass the discontinuities; smaller steps can help IsSpice find intermediate answers that are useful for finding the nonconverging point.
Solution 3. Do not use dc sweep analysis. For example, instead of specifying ".DC VCC 0 5 .1'' and "VCC 1 0," specify ".TRAN .01 1" and "VCC 1 0 PULSE 0 5 0 1." In many cases, it is more effective and efficient to use the transient analysis, by ramping the appropriate voltage and current sources, than to use the .DC analysis.
The following solutions apply to problems with transient convergence:
Solution 0. Check circuit topology and connectivity (as in solution 0 in the dc analysis).
Solution 1. Set RELTOL=.01 in the .OPTIONS statement. For example, specify ".OPTIONS RELTOL=.01." For most simulations, reducing RELTOL speeds simulation 10 to 50% with only a minor loss in accuracy. You can set RELTOL to .01 for initial simulations and then reset it when you have the simulation going the way you like it and need a more accurate answer.
Solution 2. Set ITL4=100 in the .OPTIONS statement. For example, specifying ".OPTIONS ITL4=100'' increases the number of transient iterations at each time point that IsSpice goes through before giving up.
Solution 3. Reduce the accuracy of ABSTOL and VNTOL if current and voltage levels allow. For example, specify ".OPTIONS ABSTOL=1N VNTOL=1M." You can set ABSTOL and VNTOL about eight orders of magnitude below the average voltage and current. Defaults are "ABSTOL=1PA" and "VNTOL=1UV."
Solution 4. Model your circuit realistically. Add parasitics, especially stray and junction capacitance. The idea here is to smooth any strong nonlinearities or discontinuities, which you can do by adding capacitance to various nodes and by making sure that all semiconductor junctions have capacitance. Other tips include:
Many vendors cheat by trying to "force-fit" the Spice .MODEL statement to represent a device's behavior. This is a sure sign that the vendor has skimped on quality in favor of quantity. You cannot use primitive .MODEL statements to model most devices above 200 MHz because of the effects of package parasitics, and you cannot use .MODEL statements to model most power devices because of extreme nonlinear behavior. In particular, if your vendor uses a .MODEL statement to model a power MOSFET, throw away the model. It's almost certainly useless for transient analysis.
Solution 5. Reduce the rise and fall times of PULSE sources. For example, change "VCC 1 0 PULSE 0 1 0 0 0'' to "VCC 1 0 PULSE 0 1 0 1U 1U." Again the point is to smooth strong nonlinearities. Pulse times should be realistic, not ideal. If you don't specify rise or fall times or if you specify 0, the times default to the TSTEP value in the .TRAN statement.
Solution 6. Change to gear integration. For example, specify ".OPTIONS METHOD=GEAR." You should couple gear integration with a reduction in the RELTOL value. This technique tends to produce a more stable numerical solution, while trapezoidal integration tends to produce a less stable solution. Gear integration often produces superior results for power circuitry simulations because of the high-frequency ringing and long simulation periods gear integration involves. IsSpice includes both trapezoidal and gear integration.
Special cases You can take additional steps in some cases. With MOSFETs, check the connectivity; connecting two gates to each other but to nothing else results in a PIVTOL or singular-matrix error. Also check the model level. Spice 2 does not behave properly when MOSFETs of different levels are in the same simulation.
For long transient runs, set .OPTIONS parameter ITL5 to 0 to specify that the simulation run to completion, no matter how many iterations it takes. For good reason, Spice 3 eliminates the need for both the ITL5 and LIMPTS options.
Spice 3 convergence helpers
If you're running a version of Spice based on Berkeley Spice 3, the following other options are available:
Solution 0. Use the Gminsteps option for dc convergence. For example, specify ".OPTIONS GMINSTEPS=200." The Gminsteps option adjusts the number of increments for Gmin during the dc analysis. Gmin stepping occurs automatically when there is a convergence problem. Gmin stepping is a new algorithm in Spice 3 that greatly improves dc convergence.
Solution 1. Use the Where function for dc and transient convergence. For example, specify
.control
where
.endc
The new Interactive Command Language (ICL) in IsSpice3 lets you ask for specific information about where a convergence problem is occurring. In some cases, Spice 3 does not report the node or device that is failing to converge. You normally add the Where function to the control block after a simulation fails. When you run the simulation again, you get a report of the problem area.
Solution 2. Use the ALTINIT function for transient convergence. For example, if you specify ".OPTIONS ALTINIT=1," Spice bypasses the default algorithm that's normally invoked by the UIC (use initial condition) keyword. Instead, it uses a second, more lenient algorithm. Normally, the failure of the default method causes the second algorithm to be invoked.
Author's biography
Charles Hymowitz is vice president of Intusoft, San Pedro, CA, where he is involved with product development, technical support, and marketing. He has a BSEE degree from Rutgers University, New Brunswick, NJ, and has done postgraduate work at the University of California, Los Angeles. He's a member of Tau Beta Pi, Eta Kappa Nu, and the IEEE.
References