CS-683: Advanced Computer Architecture

 

Semester: July - Nov 2016

 

Instructor: Virendra Singh

 

Class Timings:

 

Office Hours:

 

Syllabus:

 

Introduction to high performance computing, RISC philosophy and overview of pipelined architecture. Performance evaluation of pipelined architecture. Limitations of scalar pipelines, Instruction level parallelism, superscalar architecture, dynamic pipelines, superscalar techniques, performance evaluation of superscalar architectures, VLIW architecture, data-level parallelism, thread-level parallelism, simultaneous multi-threaded architectures, instruction fetch policies in multi-threaded architectures, multi-core architectures. Memory system design, storage system design.

 

References

 

  1. J.L. Hennessy, and D.A. Patterson, Computer Architecture: A quantitative approach, Fifth Edition, Morgan Kaufman Publication, 2012
  2. J.P. Shen and M.H. Lipasti, Modern Processor Design, MC Graw Hill, Crowfordsville, 2005
  3. Current Literature (Papers from ISCA, Micro, HPCA, ICCD, and IEEE Trans. on Computers, IEEE Architecture Letters)

 

 

Prerequisite: CS-305: Computer Architecture.

In case you have not taken CS-305 prior consent from Instructor is necessary.

Note: Students must watch the lecture video before coming to class

 

Lecture Schedule (Moodle Lecture Material Link, Video Lectures)

 

1.     20 July: Course Introduction

2.     24 July: Introduction to Computer Architecture

3.     26 July: Instruction set architecture

4.     02 Aug: Evolution of architectures

5.     07 Aug: RISC architecture (Single cycle, multi-cycle, and pipelined architectures)

6.     09 Aug: Pipeline hazards

7.     14 Aug: Memory system

8.     16 Aug: Cache architecture

9.     21 Aug: Beyond Pipeline

10.  23 Aug: Superscalar architecture

11.  28 Aug: Superscalar architecture: An overview

12.  30 Aug: Instruction flow optimization: Handling branches

13.  04 Sep: Branch predictors – 1

14.  06 Sep: Branch predictors - 2

15.  18 Sep: Advanced optimization in instruction flow

16.  20 Sep: register flow techniques: Register renaming and out of order execution

17.  25 Sep: Out of order execution

18.  27 Sep: Advanced data flow techniques: Instruction reuse and value prediction

19.  02 Oct: Memory data flow

20.  05 Oct: Advanced memory data flow architectures

21.  09 Oct: Limits of superscalar architectures

22.  11 Oct: Beyond ILP

23.  11 Oct: Multi-threading

24.  15 Oct: Simultaneous multithreaded (SMT) architectures

25.  16 Oct: SMT architecture: Choices

26.  16 Oct: SMT performance on various designs

27.  22 Oct: SMT architecture: OS impact and adaptive architectures

28.  23 Oct: VLIW architectures

29.  25 Oct: Multiscalar architecture

30.  26 Oct: Multi-core Architectures

31.  30 Oct: Multicore Interconnect – NOC

32.  31 Oct: Network-on-Chip

33.  3 Nov: Cache Coherence

34.  4 Nov: Cache Consistency model

35.  10 Nov: Dynamic Core architectures

36.  11 Nov: GP-GPU Architecture

37.  12 Nov: CPU-GPU Integration