Publications: List of my
publications
Recent
Publications:
In 2025
1. Rushikesh Kawale, Sonali Shukla,
Makoto Ikeda, Masahiro Fujita and Virendra Singh, `HiPeR-SM:
High Performance Reconfigurable Scalar Multiplier over NIST-P256 and CURVE25519`,
34th International Workshop on Logic & Synthesis (IWLS 2025), Verona, Italy,
June 12-13, 2025.
2.
3. Raghunandana K, Yogesh Prasad R,
Matteo Sonza Reorda, and Virendra Singh, `GPD:
Predictive control flow error detection leveraging data flow error detection
methods`, Proc. of 31st International Symposium on Online Testing and Robust
System Design (IOLTS-25), Ischia, Italy, July 7-9, 2025.
4. Varun Venkitaraman,
Shrasti Bhargava, Tejeshwar Bhagatsing
Thorawade, Keerthisagar Kokkiligadda, Rahul Kumar, Virendra Singh, `RRR: Robust
Runtime Reconfigurable Shared Cache Management Scheme for GPGPUs`, Proc. of 58th
IEEE International Symposium on Circuits and Systems 2025 (ISCAS 2025), London,
UK, May 25-28, 2025.
5. Anjum Riaz, Gaurav Kumar, Yamuna
Prasad, Satyadev Ahlawat, and Virendra Singh, “A New Hardware Trojan Attack on
Scan-obfuscated Logic-locked Circuits”, Proc. of 58th IEEE
International Symposium on Circuits and Systems 2025 (ISCAS 2025), London, UK,
May 25-28, 2025.
6. Varun Venkitaraman,
Rishabh Ravi, Tejeshwar Thorawade, Nirmal Boran, and
Virendra Singh, “SCAM: Secure shared cache partitioning to enhance throughput
of CMPs” Proc. of 22nd International Conference on Security and
Cryptography (SECRYPT 2025), Bilboa, Spain, June 11-13, 2025
7. Nikhil Kumar Parida, Sarath Babu,
Neeraj Pawar, and Virendra Singh, “EDQKD: Enhanced-Dynamic Quantum Key
Distributions with Improved Security and key rate”, Proc. of 22nd International
Conference on Security and Cryptography (SECRYPT 2025), Bilboa, Spain, June
11-13, 2025
8. Rushikesh Kawale, Sarath Babu, and
Virendra Singh, “Stegoslayer: A robust browser
integrated approach for Thwarting Stegomalware”, Proc.
of 22nd International Conference on Security and Cryptography
(SECRYPT 2025), Bilboa, Spain, June 11-13, 2025
9. Yogesh Gholap, Prajakta Yeola, Virendra Singh, “On Developing a Hybrid
Cyber-Physical Testbed for Cyber-Secure Industrial Control System” Proc. of IEEE
Latin American Conference on Internet of Things (LatinIoT-2025), Forateza, Brazil, April 2025.
10. Prakhar Diwan, Nirmal Kumar Boran, and
Virendra Singh, “Li-chen: Leveraging Coupled
Heterogeneity”, Proc. of 38th International Conference on VLSI
Design (VLSID-2025), Bangalore, India, Jan 2025
11. Aditi Gupta, Adeiza
James Onumanyi, Satyadev Ahlawat, Yamuna Prasad, and
Virendra Singh, “B-CAVE: A robust online time series change point detection
algorithm based on between-class average and variance evaluation approach”,
IEEE Trans. on Knowledge and Data Engineering (TKDE), vol. 37, no. 1, Jan 2025
In
2024
12.
Suma Sri Mandru, Srikanth Yadav Chakka, Tikaram Sanyasi, and
Virendra Singh, “MALAI: ML-based attack on learning with error (LWE) problem”, Proc.
of 20th International Conference on Information Systems Security
(ICISS 2024), Jaipur, India, Dec 2024
13.
Tarun Bisht,
Sarath Babu, and Virendra Singh, “Critical behaviour sequence monitoring for
early malware detection”, Proc. of 17th International Conference on Security
of Information Networks (SINConf-2024), Sydney, Australia, Dec 2024.
14.
Nirmal Kumar
Boran, Prakhar Diwan, Meet Udeshi, Shubhankit
Rathore, and Virendra Singh, “HIDC: Heterogeneous ISA dynamic core”, Proc. of 26th
IEEE International Conference on High Performance Computing and Communication
(IEEE HPCC 2024), Wuhan, China, Dec 2024
15.
Tejeshwar Thorawade, Prajakta Yeola, Varun Venkitaraman, and Virendra Singh, “S-Cflush:
Securing against flush-based cache timing side channel attacks”, Proc. of 36th
IEEE International Symposium on Computer Architecture and High Performance
Computing (SBAC-PAD 2024), Hawaii, USA, Nov 2024
16.
error detection
and correcting fault tolerant architecture”, Proc. of 20th IEEE
East-West Design and Test Symposium (EWDTS-2024), Yervan,
Armenia, Nov. 2024.
17.
Rohit Badjatya, Vinay, Rahul Kumar, Jaynarayan
Tudu, Masahiro Fujita, and Virendra Singh, “Physical design aware scan cell
reordering for low power testing”, Proc. of 20th IEEE East-West
Design and Test Symposium (EWDTS-2024), Yervan,
Armenia, Nov. 2024
18.
Raghunandan K K, Yogesh Prasad, Matteo Sonza Reorda,
and Virendra Singh, “TRRR: Accelerated online error detecting and correcting
fault tolerant architecture”, Proc. of 20th IEEE East-West Design
and Test Symposium (EWDTS-2024), Yervan, Armenia,
Nov. 2024
19.
Samiksha Verma,
and Virendra Singh, “SMS: Solving many RowHammer”, Proc.
of 11th International Symposium on Memory Systems (MEMSYS-24),
Washington DC, Oct 2024
20.
Sarath Babu and
Virendra Singh, “BD-MDLC: Behaviour description based enhanced malware
detection for windows environment using longformer
classifier”, Computers and Security, vol. 146, Aug 2024.
21.
Aditi Gupta, Adeiza James Onumanyi, Satyadev
Ahlawat, Yamuna Prasad, Virendra Singh, and Adnan M. Abu-Mahfouz, “DAT: A
robust discriminant analysis-based test of unimodality for unknown input
distributions”, Pattern Recognition Letters, vol. 182, April 2024
22.
Raghunandan K K, Yogesh Prasad, Matteo Sonza Reorda,
and Virendra Singh, “TCC: GPGPU architecture for instruction decoder and
control flow error detection” Proc. of 27th International Symposium
on Design and Diagnosis Electronic Circuits and Systems (DDECS-2024), Kielce,
Poland, April 2024.
23.
Aditi Gupta,
Sukanya Gupta, Adeiza James Onumanyi,
Satyadev Ahlawat, Yamuna Prasad and Virendra Singh, “A-TSPD: Autonomous two
stage algorithm for robust peak detection in online time series”, Cluster
Computing, vol. 27, March 2024
24.
Chandramani Chaudhary,
Nirmal Kumar Boran, N Sangeeth, and Virendra Singh, “GNNDLD: Graph neural
network with directional label distribution”, Proc. of 16th
International Conference on Agents and Artificial Intelligence (ICAART 2024),
Feb 2024.
25.
Rajkumar
Choudhary, Janeel Patel, and Virendra Singh, “Early execution for soft error
detection”, Proc. of 37th International Conference on VLSI Design
(VLSID-2024), Kolkata, India, Jan 2025
26.
Prakhar Diwan,
Suryakant Toraskar, Varun Venkitaraman,
Nirmal Kumar Boran, and Virendra Singh, “MIST: Many ISA scheduling technique
for heterogeneous ISA architectures”, Proc. of 37th International
Conference on VLSI Design (VLSID-2024), Kolkata, India, Jan 2024
27.
Winnie Thomas and
Virendra Singh, “Accelerating neural network inference in handwritten digit
recognition – Comparative study”, Parallel Processing Letters, vol. 34, No. 3,
2024
In
2023
28.
Tikaram Sanyasi,
Nirmal Kumar Boran, and Virendra Singh, “Sedure KNN
Computation in Cloud”, Proc. of 19th International Conference on
Information Systems Security (ICISS 2023), Raipur, India, Dec 2024
29.
Neha Hooda and
Virendra Singh, “Brutector: A probabilistic detection
model for Bruteforce attacks in SSH servers”, Proc.
of 16th International Conference on Security of Information Networks
(SINConf-2023), Jaipur, India, Dec 2023
30.
Pooja Chaudhary,
Lava Bhargava, Vinod Guna, Ashok Kumar Suhag, Masahiro Fujita, and Virendra
Singh, Proc. of Optimization of imprecise multiplier circuits by using binary
decision diagram”, Proc. of IEEE International Symposium on Smart Electronic
Systems (iSES 2023), Ahmedabad, India, Dec 2023
31.
Gowthami Konganapalle, Sonali Shukla, and Virendra Singh, “SMASh: A state encoding methodology against attacks on
finite state machines”, Proc. of 32nd EEE Asian Test Symposium (ATS
2023), Beijing, China, Oct 2023
32.
Govind Rajhans
Jadhav, Sonali Shukla, and Virendra Singh, “On attacking scan-based logic
locking schemes”, Proc. of 36th IEEE International Symposium on
Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT-2023),
Juan-Les-Pins, France, Oct 2023
33.
Raghunandan K. K,
Yogesh Prasad K. R, Matteo Sonza Reorda, and Virendra
Singh, “DDSR: An online GPGPU instruction decoder error detecting and
correcting architecture”, Proc. of 36th IEEE International Symposium
on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT-2023),
Juan-Les-Pins, France, Oct 2023
34.
Aditi Gupta, Adeiza James Onumanyi, Satyadev
Ahlawat, Yamuna Prasad, and Virendra Singh, “TSPD: A robust online time series
two stage peak detection algorithm”, Proc. of IEEE International Conference on
Service-Oriented System Engineering (SOSE 2023), Athens, Greece, July 2023
35.
Prokash Ghosh,
Yogesh Gholap, and Virendra Singh, “On-chip SRAM disclosure attack prevention
technique for SoC”, Proc. of 29th IEEE International Symposium on
On-line Testing and Robust System Design (IOLTS 2023), Chania, Greece, July
2023
36.
Raghunandan K. K,
B.K.S.V.L Varaprasad, Matteo Sonza Reorda, and Virendra Singh, “TREFU: An online error
detecting and correcting fault tolerant GPGPU architecture”, Proc. of 29th
IEEE International Symposium on On-line Testing and Robust System Design (IOLTS
2023), Chania, Greece, July 2023
37.
Sonali Shukla,
Bhavika Kumar, and Virendra Singh, “SSSN: Secured streaming scan network”,
Proc. of 24th Latin American Test Symposium (LATS’23), Veracruz,
Mexico, March 2023.
38.
Pooja Chaudhary,
Lava Bhargava, Masahiro Fujita, and Virendra Singh, “LUT based arithmetic
circuit approximation with formal guarantee on worst case relative error”,
Proc. of 24th Latin American Test Symposium (LATS’23), Veracruz,
Mexico, March 2023.
39.
Varun Venkitaraman, Ashok Sathyan, Shrihari Deshmukh, and
Virendra Singh, “Novel efficient synonym handling mechanism for virtual real
cache hierarchy”, Proc. of IEEE Design Automation and Test in Europe (DATE’23),
Antwerp, Belgium, April 2023.
In 2022
40.
Raghunandan KK,
BKSVL Varaprasad, Matteo Sonza Reorda,
and Virendra Singh, “REFU: Redundant execution with idle functional units,
fault tolerant GPGPU architecture”, Proc. of IEEE Computer Society Annual
Symposium on VLSI (ISVLSI’22), Pafos, Cyprus, July 2022.
41.
Nirmal Kumar
Boran, Pranil Joshi and Virendra Singh, “PASS-P: Performance and security
sensitive dynamic cache portioning”, 19th International Conference
on Security and Cryptography (SECRYPT’22), Lisbon, Portugal, July 2022
42.
Anishetti Venkatesh, Chandan Kumar Jha, G. Vinod, Masahiro
Fujita, and Virendra Singh, “Scalable construction of formal guaranteed LUT
based approximate multiplier with analytical worst case error bound”, 26th
International Symposium on VLSI Design and Test (VDAT’22), Jammu, India, July
2022
43.
Pooja Chaudhary,
Lava Bhargava, Masahiro Fujita, and Virendra Singh, “Synthesis of LUT based
approximate circuits with formal error guarantees”, 26th
International Symposium on VLSI Design and Test (VDAT’22), Jammu, India, July
2022
44.
Ashwin Lele,
Srivastava Jandhyala, Saurabh Gangurde, Virendra Singh, Srinivas Subramoney, and Udayan Ganguly, “Disrupting low-write
energy vs fast-read dilemma in RRAM to enable L1 instruction cache” 26th
International Symposium on VLSI Design and Test (VDAT’22), Jammu, India, July
2022.
45.
Riccardo Cantoro, Francesco Garau, Riccardo Masante,
Sandro Sartoni, Virendra Singh, and Matteo Sonza Reorda, “Exploiting post-silicon debug hardware to improve
the fault coverage of software test libraries”, 40th IEEE VLSI Test
Symposium, California, USA, April 2022.
46.
Nirmal Kumar
Boran, Shubhankit Rathore, Meet Udeshi, and Virendra
Singh, “Fine-grained scheduling in heterogeneous-ISA architecture”, IEEE
Computer Architeture letters (CAL), Vol 20, No.1,
2021.
47.
Arindam Sarkar,
Newton Singh, Varun Venkitaraman and Virendra Singh,
“DAM: Deadlock aware migration techniques for STT-RAM based hybrid caches”,
IEEE Computer Architecture Letters (CAL), 20 (1), 2021
48.
Jaynarayan T. Tudu, Satyadev Ahlawat, Sonali Shukla, and
Virendra Singh, “A framework for configurable joint-scan design-for-test
architecture”, Journal of Electronic Testing: Theory & Application (JETTA),
37(5), 2021
49.
VS Vineesh, Binod
Kumar, Rushikesh Shinde, Neelam Sharma, Masahiro Fujita, and Virendra Singh,
“Enhanced design debugging with assistance from guidance-based model checking”,
IEEE Trans. On Computer Aided Design of Integrated Circuits (TCAD), 40(5), 2021.
50.
Insha Amin,
Deepak Mishra, Ravikant Saini, and Virendra Singh, “Secrecy rate maximization
at near user in untrusted NOMA with trusted DF relay”, Proc. of 15th
International conference on advanced networks and telecom systems (ANTS’21),
Hyderabad, India, Dec 2021.
51.
Abhinish Anand, Winnie Thomas, Suryakant Toraskar,
and Virendra Singh, “Predictive warp scheduling for efficient execution in
GPGPU”, Proc. of 31st ACM Great Lakes Symposium on VLSI
(GLSVLSI’21), Virtual event, June 2021.
52.
Winnie Thomas,
Suryakant Toraskar, and Virendra Singh, “Dynamic
optimizations in GPU using Roofline model”, Proc. of IEEE International
Symposium on Circuits and Systems (ISCAS’21), Daegu, Korea, May 2021.
53.
Harsh Bhargav,
Vineesh VS, Binod Kumar, and Virendra Singh, “Enhancing testbench quality via
genetic algorithm”, Proc. of 64th IEEE International Midwest
Symposium on Circuits and Systems (MWCAS’21), East Lancing, USA, Aug 2021.
In
2021
54.
Nirmal Kumar
Boran, Shubhankit Rathore, Meet Udeshi, and Virendra
Singh, “Fine-grained scheduling in heterogeneous-ISA architecture”, IEEE
Computer Architeture letters (CAL), Vol 20, No.1,
2021.
55.
Arindam Sarkar,
Newton Singh, Varun Venkitaraman and Virendra Singh,
“DAM: Deadlock aware migration techniques for STT-RAM based hybrid caches”,
IEEE Computer Architecture Letters (CAL), 20 (1), 2021
56.
Jaynarayan T. Tudu, Satyadev Ahlawat, Sonali Shukla, and
Virendra Singh, “A framework for configurable joint-scan design-for-test
architecture”, Journal of Electronic Testing: Theory & Application (JETTA),
37(5), 2021
57.
VS Vineesh, Binod
Kumar, Rushikesh Shinde, Neelam Sharma, Masahiro Fujita, and Virendra Singh,
“Enhanced design debugging with assistance from guidance-based model checking”,
IEEE Trans. On Computer Aided Design of Integrated Circuits (TCAD), 40(5), 2021.
58.
Insha Amin,
Deepak Mishra, Ravikant Saini, and Virendra Singh, “Secrecy rate maximization
at near user in untrusted NOMA with trusted DF relay”, Proc. of 15th
International conference on advanced networks and telecom systems (ANTS’21),
Hyderabad, India, Dec 2021.
59.
Abhinish Anand, Winnie Thomas, Suryakant Toraskar,
and Virendra Singh, “Predictive warp scheduling for efficient execution in
GPGPU”, Proc. of 31st ACM Great Lakes Symposium on VLSI
(GLSVLSI’21), Virtual event, June 2021.
60.
Winnie Thomas,
Suryakant Toraskar, and Virendra Singh, “Dynamic
optimizations in GPU using Roofline model”, Proc. of IEEE International
Symposium on Circuits and Systems (ISCAS’21), Daegu, Korea, May 2021.
61.
Harsh Bhargav,
Vineesh VS, Binod Kumar, and Virendra Singh, “Enhancing testbench quality via
genetic algorithm”, Proc. of 64th IEEE International Midwest
Symposium on Circuits and Systems (MWCAS’21), East Lancing, USA, Aug 2021.
62. Abhinish Anand, Winnie Thomas, Suryakant Toraskar, and Virendra Singh, “Predictive warp scheduling
for efficient execution in GPGPU”, 31st ACM Great Lake Symposium on
VLSI (GLSVLSI`21), June 2021.
63. Winnie Thomas, Suryakant Toraskar,
and Virendra Singh, “Dynamic optimization in GPU using Roofline model”, Proc.
of International Symposium on Circuits and Systems (ISCAS`21), Daegu,
Korea, May 2021
64. Arindam Sarkar, Newton, Varun Venkitaraman,
and Virendra Singh, “DAM: Deadlock aware
migration techniques for STT-RAM based hybrid caches”, IEEE
Computer Architecture Letters (CAL), 2021
65. Nirmal Kumar Boran, Shubhankit Rathore, Meet Udeshi, and Virendra Singh,
"Fine-grained Scheduling in Heterogeneous-ISA Architectures", IEEE
Computer Architecture Letters (CAL), Vol. 20, No.1, Jan 2021
66. Jaynarayan Tudu, Satyadev Ahlawat, Sonali Shukla, and Virendra
Singh, `A framework for configurable for joint-scan design-for-test
architecture`, Journal of Electronic Testing: Theory and Application (JETTA), 2021
67. Abhinish Anand, Winnie Thomas, Suryakant Toraskar, and
Virendra Singh, `Predictive warp scheduling for efficient execution in GPGPU`,
31st ACM Great Lake Symposium on VLSI (GLSVLSI`21), June
2021.
68. Winnie Thomas, Suryakant Toraskar,
and Virendra Singh, `Dynamic optimization in GPU using Roofline model`, Proc.
of International Symposium on Circuits and Systems (ISCAS`21), Daegu,
Korea, May 2021
69. Vineesh VS, Binod Kumar, Rushikesh Shinde, Neelam Sharma, Masahiro
Fujita, and Virendra Singh, `Enhanced design debugging with assistance from guidance based model checking`, IEEE Transaction on Computer
Aided Design (TCAD), Vol. 14, No. 5, May 2021
70. Arindam Sarkar, Newton, Varun Venkitaraman, and
Virendra Singh, `DAM: Deadlock aware migration techniques for STT-RAM based
hybrid caches`, IEEE Computer Architecture Letters (CAL),
Vol 20, No. 1, Jan 2021
71. Nirmal Kumar Boran, Shubhankit Rathore, Meet Udeshi, and Virendra Singh,
`Fine-grained Scheduling in Heterogeneous-ISA Architectures`, IEEE Computer
Architecture Letters (CAL), Vol. 20, No.1, Jan 2021
72. Harsh
Bhargav, Vineesh VS, Binod Kumar and Virendra Singh, `Enhancing testbench
quality via genetic algorithm`, Proc. of Mid-West Symposium on Circuits and
Systems (MWSCAS) 2021
In 2020
73. Newton, Virendra Singh, and Trevor E.
Carlson, `PIM-GraphSCC: PIM-based Graph Processing using Graph's Community
Structures`, IEEE Computer Architecture Letters (CAL), 2020
74. Vinod Guna, Vineesh V.S, Jaynarayan Tudu,
Masahiro Fujita, and Virendra Singh, `LUT-based circuit approximation with
targeted error guarantees`, 29th IEEE Asian Test Symposium (ATS20), Penang, Malaysia, Nov 2020
75. Binod Kumar, Jay Adhaduk,
Kanad Basu, Masahiro Fujita, and Virendra Singh, `A methodology to capture fine
grained internal visibility during multi-session silicon debug`, IEEE
Transaction on Very Large Scale Integrated Systems (TVLSI), vol. 28, No.
4, April 2020
76. Antara Ganguly, Shankar Balachandran,
Anant Nori, Virendra Singh and Sreenivas Subramoney, `Characterization of data
generating neural network workloads on x86 server architecture`, Workshop on
Benchmarking Machine Learning Loads (MLBench20),
Boston, Massachusetts, USA, April 2020.
77. Antara Ganguly, Shankar Balachandran,
Anant Nori, Virendra Singh and Sreenivas Subramoney, `Characterization of data
generating neural network application on x86 server architecture`, IEEE
International Symposium on Performance Analysis of Systems and Software (ISPASS), Boston, Massachusetts, USA,
April 2020.
78. Jiji Angel and Virendra Singh, `On the DSA key recovery attack with
variable partial nonces known`, 3rd ISEA International Conference on
Security and Privacy (ISEA-ISAP),
Guwahati, India, Feb 2020.
79. Binod Kumar, Swapaniel Thakur, Kanad Basu,
Masahiro Fujita, and Virendra Singh, `A low overhead methodology for validating
memory consistency models in chip multiprocessors`, 33rd
International Conference on VLSI Design (VLSID-20),
Bangalore, India, Jan 2020.
In 2019
80. Binod Kumar, Atul Kumar Bhosale,
Masahiro Fujita, and Virendra Singh, `Validating multi-processor cache
coherence mechanisms under diminished observability`, 28th IEEE
Asian Test Symposium (ATS19), Kolkata, India, Dec 2019.
81. Vineesh VS, Binod Kumar, Rushikesh
Shinde, Akshay Kumar Jaiswal, Harsh Bhargava, and Virendra Singh, `Orion: A
technique to prune state space search directions for guidance based formal
verification`, 28th IEEE Asian Test Symposium (ATS19),
Kolkata, India, Dec 2019.
82. Rushikesh Shinde, Binod Kumar,
Vineesh VS, and Virendra Singh, `Aquila: A methodology for achieving
fine-grained bug localization during design verification`, 20th IEEE
International Workshop on RTL and High Level Testing (WRTLT), Kolkata,
India, Dec 2019.
83. Raj Kumar Choudhary, Newton Singh,
Harideep Nair, Rishabh Rawat and Virendra Singh, `Freeflow Core: Enhancing
Performance of In-order Cores with Energy Efficiency`, 37th IEEE International
Conference on Computer Design (ICCD-2019) , Abu Dhabi, UAE, Nov 17-20,
2019
84. Varun Venkitaraman, Ashok Sathyan and
Virendra Singh, `CBIT - A Synonym Handler for Low-latency and Energy-efficient
Cache Hierarchy`, 37th IEEE International Conference on Computer Design
(ICCD-2019), Abu Dhabi, UAE, Nov 2019. (Poster)
85. Ayush Agrawal and Virendra Singh,
`O-Factor: Opportunistic Out of Order Scheduling for GP-GPUs`, 37th IEEE
International Conference on Computer Design (ICCD - 2019), Abu Dhabi, UAE, Nov
2019 (Poster)
86. Antara Ganguly, Shankar
Balachandran, Anant Nori, Virendra Singh, and Sreenivas Subramoney,
`Characterization of data movement issues in generation-based neural network
applications on x86 CPU architecture`, The International Symposium on Memory
System (MEMSYS-2019), Oct 2019
87. Binod Kumar, Masahiro Fujita, and
Virendra Singh, `SAT-based Silicon Debug of
Electrical Errors under Restricted Observability Enhancement`, Journal of
Electronic testing: Theory and Applications, Vol. 35, No. 5, October 2019
88. Antara Ganguly, Rajiv Muralidhar,
Virendra Singh and Masahiro Fujita, `Towards Energy-efficient Architectures for
Deep Learning`, European Conference on Machine Learning (ECML-PKDD) 2019 -
Green Data Mining Workshop, Wurzburg, Germany, September 2019
89. Jaidev Shenoy, Kushal Kamal, Kelly
Ockunzzi, and Virendra Singh, `Test cost reduction through increase in
multi-site testing with reduced scan-out pins`,3rd International
Test Conference Asia (ITC-Asia), Tokyo, Sep 2019
90. Shoba Gopalkrishnan and Virendra
Singh, `Soft-error reliable architectures for future microprocessors`, IET
Computers and Digital Techniques, Aug 2019.
91. Satyadev Ahlawat, Kailash Ahirwar,
Jaynarayan Tudu, Masahiro Fujita, Virendra Singh, `Securing Scan through
Plain-text Restriction`, 25th IEEE International Symposium on On-Line
Testing and Robust System Design, Rhode Island, Greece, July 2019
92. Jaidev Shenoy, Kushal Kamal, Kelly
Ockunzzi, and Virendra Singh, `Test cost reduction through increase in
multi-site testing with reduced scan-out pins`,3rd International
Test Conference India (ITC-India), Bangalore, Jul 2019
93. Antara Ganguly, Virendra Singh, Rajiv
Muralidhar and Masahiro Fujita, `Towards Energy Efficient non-von Neumann
Architectures for Deep Learning`, 20th International Symposium on
Quality Electroncs Design (ISQED-2019), Santa Clara, USA, March 2019
94. Binod
Kumar, Masahiro Fujita and Virendra Singh, "A Methodology for SAT-based
Electrical Error Debugging during Post-silicon Validation", 32nd
International Conference on VLSI Design (VLSID-19)
2019, Delhi, Jan 2019
95. Jaidev
Shenoy, Virendra Singh, Kelly Ockunzzi and Kushal
Kamal, "On-chip MISR compaction technique to reduce diagnostic effort and
test time", 32nd International Conference on VLSI Design (VLSID-19) 2019, Delhi, Jan 2010
In 2018
96. Antara
Ganguly, Virendra Singh, Rajiv Muralidhar, and Masahiro Fujita, "Memory
system requirements for convolutional neural networks", International
Symposium on Memory Systems (MEMSYS-2018),
Washington DC, USA, October 2018
97. Satyadev
Ahlawat, Darshit Vaghani, Naveen Bazard, and Virendra Singh, "Using MISR
as countermeasure against scan based side channel attacks", IEEE
International East-West Design and Test Symposium (EWDTS-2018), Kazan, Russia, September 2018
98. Satyadev
Ahlawat, Jaynarayan Tudu, Anzhela Matrosova,
and Virendra Singh, "A High Performance Scan Flip-Flop Design for
Serial and Mixed Mode Scan Test", IEEE Transactions on Device and
Materials Reliability (TDMR), Vol. 18, No. 2, pp. 321-331, June 2018
99. Ankit
Jindal, Binod Kumar, Masahiro Fujita, and Virendra Singh, "Silicon
debug with maximally expanded internal observability using nearest neighbour algorithm", IEEE Computer Society Annual
Symposium on VLSI (ISVLSI) 2018, Hongkong, SAR, China, July 2018
100.
Suhit Pai, Newton, and Virendra Singh, "AB-Aware:
Application Behavior Aware Management of Shared Last Level Caches", 28th
ACM Great Lakes Symposium on VLSI (GLSVLSI) 2018, Chicago, Illinois,
USA, May 23-25, 2018
101.
Darshit Vaghani, Satyadev Ahlawat, Jaynarayan
Tudu, Masahiro Fujita, and Virendra Singh, "On Securing Scan Design
Through Test Vector Encryption", 51st IEEE International
Symposium on Circuits and Systems (ISCAS) 2018, Florence, Italy, May
2018
102.
Nihar Hage, Satyadev Ahlawat, and Virendra Singh,
"In-situ Monitoring for Slack Time Violation Without Performance
Penalty", 51st IEEE International Symposium on Circuits and
Systems (ISCAS) 2018, Florence, Italy, May 2018
103.
Rohini Gulve and Virendra
Singh, "ATPG Power Guards: On
Limiting the Test Power below Threshold", Proc. of Design
Automation and Test in Europe (DATE), Dresden, Germany, March 2018
104.
Toral Shah, Anzhela Matrosova,
Masahiro Fujita, and Virendra Singh, "Multiple Stuck-at Fault Testability
Analysis of ROBDD Based Combinational Circuit Design", Journal of
Electronic Testing: Theory and Application (JETTA), Vol. 34, No. 1, Feb 2018.
In 2017
105.
Ankush Srivastava, Virendra Singh, Adit
Singh, and Kewal Saluja, "A reliability
aware methodology to isolate timing critical paths under aging",
Journal of Electronic Testing: Theory and Application (JETTA), Vol. 33, No. 6, pp. 721-739, Dec 2017.
106.
Newton, Sujit Mahto, Suhit Pai, and
Virendra Singh, "DAAIP: Deadblock Aware
Adaptive Insertion Policy for High Performance Caching", 35th
International Conference on Computer Design (ICCD), Boston Marriot Newton,
Boston, MA, USA, November 2017
107.
Binod Kumar, Kanad Basu, Masahiro Fujita and Virendra
Singh, "RTL level trace signal selection and coverage estimation during
post-silicon validation", 19th IEEE International High Level
Design Validation and Test Workshop (HLDVT),
Santa Cruz, CA, USA, October 2017
108.
Satyadev Ahlawat, Darshit Vaghani, Jaynarayan
Tudu, and Virendra Singh, `On Securing Scan Design from Scan-Based
Side-Channel Attacks`, 26th IEEE Asian Test Symposium (ATS), Taipei, Taiwan, Nov 2017
109.
Ankush Srivastava, Adit
Singh, Virendra Singh, and Kewal K. Saluja, `Exploiting path delay test generation to develop better TDF tests for
small delay defects`, 48th IEEE International Test Conference
(ITC), Texas, USA, Nov 2017
110.
Shoba Gopalkrishnan and Virendra Singh, `REMORA: A hybrid low-cost soft-error
reliable fault tolerant architecture`, 30th IEEE
International Symposium on Defect and Fault Tolerance in VLSI and
Nanotechnology Systems (DFT), Cambridge, UK, October 2017
111.
Satyadev Ahlawat, Darshit Vaghani, and Virendra Singh,
`Preventing scan-based side-channel
attacks through key masking`, 30th IEEE International
Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT),
Cambridge, UK, October 2017
112.
Binod Kumar, Kanad Basu, Ankit Jindal, Masahiro
Fujita, and Virendra Singh, `Improving
post-silicon error detection with topological selection of trace signals`,
25th IEEE/IFIP International Conference on Very Large Scale Integratiion (VLSI-SoC), Abu Dhabi, UAE, October
2017
113.
Rohini Gulve, Anshu Goel,
and Virendra Singh, `PHP: Power hungry pattern generation at higher abstraction
level`, 15th IEEE East-West Design and Test Symposium (EWDTS), Novi Sad, Serbia, Sep 2017
114.
Vineesh VS, Nihar Hage, Kartik B, and Virendra Singh,
`On achieving full functional coverage for forwarding units of pipelined
processors`, 15th IEEE East-West Design and Test Symposium (EWDTS), Novi Sad, Serbia, Sep 2017
115.
Abhishek Rajgadia, Newton Singh, and Virendra Singh, `EEAL: Processors
performance enhancement through early execution of aliased loads`, 27th
ACM Great Lakes Symposium on VLSI (GLSVLSI)
2017, Alberta, Canada, May 2017
116.
Binod Kumar,
Ankit Jindal, Masahiro Fujita, and Virendra Singh, `Combining restorability and
error detection ability for effective trace signal selection`, 27th
ACM Great Lakes Symposium on VLSI (GLSVLSI)
2017, Alberta, Canada, May 2017
117.
Nihar Hage,
Rohini Gulve, Masahiro Fujita, and Virendra Singh,
`Instruction-based self-test for delay faults maximizing operating
temperature`, 23rd IEEE International Symposium on On-Line Testing
and Robust System Design (IOLTS)
2017, Thessaloniko, Greece, July 2017
118.
Binod Kumar,
Ankit Jindal, Jaynarayan Tudu, Brajesh Pandey, and
Virendra Singh, `Revisiting Random Access Scan for enhancement of post silicon
observability`, 23rd IEEE International Symposium on On-Line Testing
and Robust System Design (IOLTS)
2017, Thessaloniko, Greece, July 2017
119.
Toral Shah,
Anzhela Matrosova, and Virendra Singh, `Test pattern
generation to detect multiple faults in ROBDD based combinational circuits, 23rd
IEEE International Symposium on On-Line Testing and Robust System Design (IOLTS) 2017, Thessaloniko,
Greece, July 2017
120.
Satyadev
Ahlawat, Darshit Vaghani, and Virendra Singh, `An efficient test technique to
prevent scan-based side-channel attacks`, 22nd IEEE European Test
Symposium (ETS) 2017, Limassol,
Cyprus, May 2017
121.
Satyadev
Ahlawat, Darshit Vaghani, Rohini Gulve, and Virendra
Singh, `A low cost technique for scan chain diagnosis`, 50th IEEE Inaternational Symposium on Circuits and Systems (ISCAS) 2017, Baltimore, MD, USA, May
2017
122.
Binod Kumar, Ankit Jindal,
Masahiro Fujita and Virendra Singh, `Post-silicon Observability Enhancement
with Topology Based Trace Signal Selection`, 18th IEEE Latin American Test
Symposium (LATS) 2017, Bogota, Colombia, March 2017
123.
Ankush Srivastava, Virendra
Singh, Adit Singh and Kewal Saluja, `Identifying High
Variability Speed-Limiting Paths under Aging`, 18th IEEE Latin American Test
Symposium (LATS) 2017, Bogota, Colombia, March 2017
124.
Toral Shah, Anzhela Matrosova, Binod Kumar, Masahiro Fujita and Virendra Singh,`Testing Multiple Stuck-at
Faults of ROBDD Based Combinational Circuit Design`, 18th IEEE Latin American
Test Symposium (LATS) 2017, Bogota, Colombia, March 2017
125.
Nihar Hage,
Rohini Gulve, Masahiro Fujita, and Virendra Singh,
`On testing of superscalar processors in functional mode for delay faults`, 30th
International conference on VLSI Design (VLSID)
2017, Hyderabad, Jan 2017
126.
Binod Kumar,
Ankit Jindal, Virendra Singh, and Masahiro Fujita, `A methodology for trace
signal selection to improve error detection in post silicon validation`, 30th
International conference on VLSI Design (VLSID)
2017, Hyderabad, Jan 2017
In 2016
127.
Shoba Gopalkrishnan
and Virendra Singh, `REMO: Redundant execution with minimum area, power,
performance overhead fault tolerant architecture`, 22nd IEEE
International Symposium on Online Testing and Robust System Design (IOLTS) 2016, Catalunya, Spain, July
2016
128.
Satyadev
Ahlawat, Jaynarayan Tudu, Anzhela Matrosova,
and Virendra Singh, `A high performance scan flip-flop design for serial and
mixed mode scan test` 22nd IEEE International Symposium on Online
Testing and Robust System Design (IOLTS)
2016, Catalunya, Spain, July 2016
129.
Binod Kumar, Ankit Jindal, Jaynarayan
Tudu, and Virendra Singh, `A methodology for post silicon debug utilizing
progressive random access scan architecture`, 17th IEEE Workshop on
RTL and High Level Testing (WRTLT) 2016, Hiroshima, Japan, Nov 2016
130.
Rohini Gulve and Virendra
Singh, `R-fill: Timing aware capture power reduction using ZOLP`, 17th
IEEE Workshop on RTL and High Level Testing (WRTLT) 2016, Hiroshima, Japan, Nov
2016
131.
Ankush Srivastava, Virendra Singh, Adit
Singh, and Kewal Saluja, `Path-based approach to identify timing critical paths
under aging, 17th IEEE Workshop on RTL and High Level
Testing (WRTLT) 2016, Hiroshima, Japan, Nov 2016
132.
Nirmal Kumar Boran, Rameshwar Prasad Meghwal, Kuldeep
Sharma, Binod Kumar, and Virendra Singh, ` Performance modelling of heterogeneous ISA multicore
architecture`, 14th
IEEE East-West Design and Test Symposium (EWDTS)
2016, Yerevan, Armenia, Oct 2016
133.
Toral Shah,
Virendra Singh and Anzhela Matrosova, `ROBDD based
path delay fault testable combinational circuit synthesis`, 14th
IEEE East-West Design and Test Symposium (EWDTS)
2016, Yerevan, Armenia, Oct 2016
134.
Satyadev Ahlawat, Darshit Vaghani, Rohini Gulve, and Virendra Singh, `Enabling LOS delay test with
slow scan enable`, 14th
IEEE East-West Design and Test Symposium (EWDTS)
2016, Yerevan, Armenia, Oct 2016
135.
Rohini Gulve and Virendra Singh, `ILP Based Don`t Care Bits
Filling Technique For Capture Power Reduction`, 14th IEEE East-West
Design and Test Symposium (EWDTS) 2016,
Yerevan, Armenia, Oct 2016
136.
Binod Kumar,
Boda Nehru, Brajesh Pandey, Jaynarayan T Tudu, and
Virendra Singh, `A technique for low power, stuck-at fault diagnosable and
reconfigurable scan architecture`, 14th IEEE East-West Design and
Test Symposium (EWDTS) 2016,
Yerevan, Armenia, Oct 2016
137.
Binod Kumar, Ankit Jindal and Virendra Singh, `A trace
signal selection algorithm for improved post silicon debug`, 14th IEEE East-West Design
and Test Symposium (EWDTS) 2016,
Yerevan, Armenia, Oct 2016
In 2015
138.
Parth Lathigara, Shankar Balachandran, and Virendra Singh,
`Application behavior aware re-reference interval prediction for LLC`, 33rd
IEEE International Conference on Computer Design (ICCD) 2015, New York, USA, October 2015
139.
Ankush
Srivastava, Virendra Singh, Adit Singh, and Kewal
Saluja, `A methodology for identifying high timing variability paths in complex
designs`, 24th IEEE Asian Test Symposium (ATS) 2015, Mumbai, India, Nov 2015
140.
Satyadev
Ahlawat, Jaynarayan Tudu, Virendra Singh, and Anzhela
Matrosova, `A new scan flip flop design to eliminate
performance penalty of scan`, 24th IEEE Asian Test Symposium (ATS) 2015, Mumbai, India, Nov 2015
141.
Adithyalal P.M, Shankar Balachandran, and Virendra Singh, `A
soft error resilient low leakage SRAM cell design`, 24th IEEE Asian
Test Symposium (ATS) 2015, Mumbai,
India, Nov 2015
142.
Toral Shah, Virendra Singh, and Anzhela Matrosova, `BDD based PDF testable combinational circuit
design`, 16th IEEE Workshop on RTL and High Level Testing (WRTLT)
2015, Mumbai, Nov 2015
143.
Toral Shah,
Anzhela Matrosova, and Virendra Singh, `PDF
testability of a combinational circuit derived by covering ROBDD nodes by
Invert-And-Or graph,` 19th International
Symposium on VLSI Design and Test (VDAT) 2015, Ahmedabad, India, May 2015
In 2014
144.
D. Nikolov, U. Ingelsson, V. Singh, and E. Larsson,
`Evaluation of level of confidence and optimization of roll-back recovery with
check pointing for real time systems`, Microelectronics Reliability, vol. 54,
2014, pp. 1022-1049.
145.
Jaynarayan Tudu and
Virendra Singh, `Guided shifting of test patterns to minimize the test time in
serial scan,` 15th IEEE Workshop on RTL and
High Level Testing (WRTLT14) 2014, Hangzhou, China,
Nov 2014
146.
Prashant Singh, Toral Shah, and Virendra Singh, `An
improved single input change based built-in-self-test for delay testing,` 15th IEEE Workshop on RTL and High Level Testing (WRTLT14) 2014, Hangzhou, China, Nov 2014
147.
Lokesh Siddhu,
Amit Mishra, and Virendra Singh, `Operand isolation circuit with reduced
overhead for datapath design`, 27th
International Conference on VLSI Design (VLSID)
2014, Mumbai, India, Jan 2014
148.
Anzhela Matrosova, Evgenii Mitrofanov, and Virendra Singh, `Fully
delay testable sequential circuit design`, 5th IEEE International
Workshop on Reliability Aware Stystem Design and Test
(RASDAT), Mumbai, India, Jan 2014
In 2013
149.
Jaynarayan Tudu, Deepak Malani, and Virendra Singh, ` Level
accurate peak activity estimation in combinational circuits using BILP`, 17th
International Symposium on VLSI Design and Test (VDAT), Jaipur, India, July, 2013
150.
Anzhela Matrosova, Evgenii Mitrofanov, and Virendra Singh, `Delay
testable sequential circuit design`, 11th IEEE East-West Design and
Test Symposium (EWDTS), Rostov,
Russia, Aug 2013
In 2012
151.
Suraj Sindia,
Vishwani D. Agrawal, and Virendra Singh, `Parametric fault testing of
non-linear analog circuits based on polynomial and v-transform coefficients`,
Journal of Electronic Testing: Theory and Applications (JETTA), Vol. 28, No. 5, pp. 557-571, 2012
152.
Suraj Sindia,
Vishwani D. Agrawal, and Virendra Singh, `Defect level and fault coverage in
coefficient based analog circuit testing`, Journal of Electronic Testing:
Theory and Applications (JETTA),
Vol. 28, No. 4, pp. 541-549, 2012
153.
Satdev, Ashok Suhag, Jaynarayan Tudu, and Virendra
Singh, `Power aware scan flip-flop design for scan test`, 13th IEEE
Workshop on RTL and High Level testing (WRTLT)
2012, Niigata, Japan, Nov 2012
154.
Pawan Kumar,
and Virendra Singh, `Efficient regular expression pattern matching for network
intrusion detection system using modified word based automata`, 5th
ACM International Conference on Security of Information and Networks (SIN) 2012, Jaipur, India, Oct 2012
155.
Indira Rawat,
M.K. Gupta, and Virendra Singh, `Scheduling test for 3D SOCs with temperature
constraints`, 10th IEEE International East West Design and Test
Symposium (EWDTS) 2012, Kharkov, Ukrain, Sep 2012
156.
A. Matrosova, E. Nikolaeva, D. Kudin, and V. Singh, `PDF
testability of circuits derived by special covering ROBDDs with gates`, 10th
IEEE International East West Design and Test Symposium (EWDTS) 2012, Kharkov, Ukrain, Sep 2012
157.
A. Matrosova, E. Nikolaeva, D. Kudin, and V. Singh, `PDF
testability of circuits derived by special covering ROBDDs with gates`, 10th
IEEE International East West Design and Test Symposium (EWDTS) 2012, Kharkov, Ukrain, Sep 2012
158.
Mohammed
Shayan, Virendra Singh, Adit Singh, and Masahiro
Fujita, `SEU tolerant robust memory cell design`, 18th IEEE
International On-Line Testing Symposium (IOLTS)
2012`, Sitges, Spain, June 2012
159.
Jaynarayan Tudu, Deepak Malani, and Virendra Singh, `ILP based
approach for input vector controlled toggle maximization in combinational
circuits`, 16th International Symposium on VLSI Design and Test (VDAT) 2012, Kolkata, India, July 2012
160.
Mohammad
Shayan, Virendra Singh, Adit Singh, and Masahiro
Fujita, `SEU tolerant robust latch design`, 16th International
Symposium on VLSI Design and Test (VDAT)
2012, Kolkata, India, July 2012
161.
Indira Rawat, M.K. Gupta,
and Virendra Singh, `Thermal aware test scheduling of 3D SoCs`, 5th
IEEE International Workshop on Impact of Low Power Design on Test and
Reliability (LPonTR) 2012, Annecy, France, May 2012
162.
Suraj Sindia,
Vishwani D. Agrawal, and Virendra Singh, `Impact of process variation on
computers used for image processing`, IEEE International Symposium on Circuits
and Systems (ISCAS) 2011, Seoul,
Korea, May 2012.
163.
Prasanth V., Rubin Parekhji, and Virendra Singh,
`Derating based hardware optimizations in soft error tolerant designs`, 30th
IEEE VLSI Test Symposium (VTS) 2012,
Hawai, USA, April 2012.
164.
Vijay Sheshadri, Prasanth V., Rubin Parekhji,
Vishwani D. Agrawal, and Virendra Singh, `Evaluating impact of soft errors in
embedded system`, IEEE International Workshop on Reliability Aware System
Design and Test (RASDAT) 2012, Hyderabad, India, Jan 2012.
165.
Satdev Ahlawat, Virendra Singh, Shashidhar Bapat, and Karthik Madhugiri, `Low power scan flip-flop design to eliminate
output gating overhead for critical paths`, IEEE International Workshop
on Reliability Aware System Design and Test (RASDAT) 2012, Hyderabad, India,
Jan 2012.
166.
Mohammed Shayan, Virendra Singh, Adit Singh, and
Masahiro Fujita, `A highly robust and cost effective SEU tolerant memory cell`,
IEEE International Workshop on Reliability Aware System Design and Test
(RASDAT) 2012, Hyderabad, India, Jan 2012.
In 2011
167.
Pramod
Subramanyan, Virendra Singh, Kewal Saluja, and Erik Larsson, `Adaptive
execution assistance for multiplexed fault-tolerant chip multiprocessors`, 29th
IEEE International Conference on Computer Design (ICCD) 2011, Amherst, MA, USA, October 2011
168.
Mohammed Abdul
Razzaq, Virendra Singh, and Adit Singh, `SSTKR:
Secure and testable scan design through test key randomization`, 20th
IEEE Asian Test Symposium (ATS)
2011, New Delhi, India, Nov. 2011
169.
Suraj Sindia,
Vishwani Agrawal, and Virendra Singh, `Test and diagnosis of analog circuits
using moment generating functions`, 20th IEEE Asian Test Symposium (ATS) 2011, New Delhi, India, Nov. 2011
170.
Manas Puthal, Virendra Singh, MS Gaur and Vijay Laxmi,
`C-Routing: An adaptive hierarchical NoC routing methodology`, 19th
IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC) 2011, Hongkong, China,
October 2011
171.
Harsh Gidra,
Israrul Haque, Nitin Kumar, M. Sargurunathan,
M.S. Gaur, Vijay Laxmi, Mark Zwolinski, and Virendra Singh, `Parallelizing
TUNAMI-N1 using GP-GPU`, 13th IEEE International Conference on High
Performance Computing and communication (HPCC) 2011, Banff, Canada, September
2011.
172.
Anzhela Matrosova, Virendra Singh, Alexey Melnikov, and Ruslan Mukhamedov, `Selection of state variables for partially
enhanced scan`, 9th IEEE East-West Design and Test Symposium (EWDTS) 2011, Sevastopol, Ukraine,
September 2011
173.
Mohammad Abdul
Razzaq, Alok Baluni, Ram Rakesh Jangir, Virendra
Singh, and Masahiro Fujita, `On synthesis of degradation aware circuits at
higher level of abstraction`, 9th IEEE East-West Design and Test
Symposium (EWDTS) 2011, Sevastopol,
Ukraine, September 2011.
174.
Pawan Kumar and
Virendra Singh, Efficient regular expression pattern matching using cascaded
automata architecture for network intrusion detection system`, 9th
IEEE East-West Design and Test Symposium (EWDTS)
2011, Sevastopol, Ukraine, September 2011.
175.
V. Prasanth,
Virendra Singh, and Rubin Parekhji, `Reduced overhead
soft error mitigation methodology using error control coding technique`, 17th
IEEE International On-Line Test Symposium (IOLTS)
2011, Athens, Greece, July 2011.
176.
Dimitar
Nikolov, Urban Ingelsson, Virendra Singh, and Erik Larsson, `Level of
confidence evaluation and its usage for roll-back recovery and checkpoint
optimization`, Workshop on Dependable and Secure Nanocomputing (WDSN) 2011, Hongkong, China, May 2011
177.
Vinutha Konandur, Virendra Singh, MS Gaur, and Anzhela Matrosova, `Fault Grading at Higher Level of Abstraction`,
IEEE International Workshop on Processor Verification, Test and Debug (IWPVTD) 2011, Trondheim, Norway, May
2011
178.
A. Matrosova, S. Ostanin, A. Milnikov, and Virendra Singh, `Using AND-OR tree for path
delay faults`, IEEE International
Workshop on Processor Verification, Test and Debug (IWPVTD) 2011, Trondheim, Norway, May 2011
179.
Dimitar
Nikolov, Urban Ingelsson, Virendra Singh, and Erik Larsson, `Study on level of
confidence for rollback recovery with check-pointing`, Workshop on
Dependability Issues in Deep-submicron Technologies (DDT) 2011, Trondheim, Norway, May 2011
180.
Suraj Sindia,
Vishwani Agrawal, and Virendra Singh, `Nonlinear analog circuit test and diagnosisunder process variation using V-transform
coefficients`, 29th IEEE VLSI Test Symposium (VTS), 2011, California, USA, May 2011
181.
Suraj Sindia,
Vishwani Agrawal, and Virendra Singh, `Testing linear and non-linear analog
circuits using moment generation functions`, 12th IEEE Latin American Test
Workshop (LATW) 2011, Porto de Galinhas, Brazil, March 2011
182.
Chao Han, Adit Singh, and Virendra Singh, `Efficient partial enhanced
Scan for high coverage delay testing`, 2011 Joint IEEE International Conference
on Industrial Technology and 43rd Southeastern Symposium on System
Theory (ICIT-SSST) 2011, Auburn,
USA, March 2011
183.
Suraj Sindia,
Vishwani Agrawal, and Virendra Singh, `Distinguishing process variation induced
faults from manufacturing defects in analog circuits using V-transform
coefficients`, 2011 Joint IEEE International Conference on Industrial
Technology and 43rd Southeastern Symposium on System Theory (ICIT-SSST) 2011, Auburn, USA, March
2011
184.
Sudipta Sarkar,
Anubhav Adak, Virendra Singh, Kewal Saluja, and Masahiro Fujita, `SEU tolerant
SRAM cell`, International Symposium on Quality Electronic Design (ISQED) 2011, Santa Clara, CA, USA,
March 2011
185.
Naveen
Choudhary, M.S. Gaur, Vijay Laxmi, and Virendra Singh, `Traffic aware topology
generation methodology for application specific NoC`, IEEE International
Symposium on Electronic Design, Test and Application (DELTA) 2011, Queens Town, New Zealand, Jan 2011
186.
Navaneeth Rameshan, Mark Zwolinski, Vijay Laxmi, M.S. Gaur, Virendra
Singh, and Lalith P., `Acceleration of functional validation using GPGPU`, IEEE
International Symposium on Electronic Design, Test and Application (DELTA) 2011, Queens Town, New Zealand,
Jan 2011
In 2010
187.
[Book Chapter] Dimitar Nikolov, Mikael Vayrynen, Urban Ingelson, Virendra Singh, and Erik Larsson,
`Optimizing Fault Tolerance for Multi-Processor System-on-Chip`, Design and Test Technology for Dependable
Systems-on-Chip, Editors: Raimund Ubar, Jaan
Raik, Heinrich Theodor Vierhaus, 2010, Hardcover,
ISBN:978-1-6096-0212-3.
188.
Sudipta Sarkar,
Anubhav Adak, Virendra Singh, Kewal Saluja, and Masahiro Fujita, `SEU tolerant
SRAM for FPGA application`, International Conference on Field Programmable
Technology (FPT) 2010, Beijing, Dec
2010
189.
Amit Mishra,
Nidhi Sinha, Satdev, Virendra Singh, Sreejit
Chakravarty, and Adit Singh, `A modified scan
flip-flop for test power reduction`, 19th IEEE Asian Test Symposium
(ATS) 2010, Shanghai, China, Dec
2010
190.
Jaynarayan Tudu, Erik Larsson, and Virendra Singh, `Test
Scheduling of modular system-on-chip under capture power constraints`, 11th
IEEE Workshop on RTL and High Level Test (WRTLT)
2010, Shanghai, China, Dec 2010
191.
Naveen
Choudhary, M.S. Gaur, Vijay Laxmi, and Virendra Singh, `Energy Aware Design
Methodologies for Application Specific NoC`, 28th Norchip Conference (NORCHIP),
2010, Tampere, Finland, Nov 2010
192.
Anzhela Matrosova, Valeriy Lipsky, Aleksey Melnikov, and Virendra
Singh, `Path delay faults and ENF`, IEEE East-West Design and Test Symposium (EWDTS) 2010, St. Petersburg, Russia,
Sep 2010
193.
Vinay N.S,
Indira Rawat, Erik Larsson, M.S. Gaur, and Virendra Singh, `Thermal aware test
scheduling for stacked multi-chip modules`, IEEE East-West Design and Test
Symposium (EWDTS) 2010, St.
Petersburg, Russia, Sep 2010.
194.
K.R. Vinutha,
Virendra Singh, Anzhela Matrosova, and M.S. Gaur,
`Fault grading using instruction-execution graph`, IEEE East-West Design and
Test Symposium (EWDTS) 2010, St.
Petersburg, Russia, Sep 2010.
195.
Adit Kajala, Gayaprasad Sinsinwar, Rahul Choudhary, Jaynarayan
Tudu, and Virendra Singh, `On selection of state variables for delay test of
identical functional units`, IEEE East-West Design and Test Symposium (EWDTS) 2010, St. Petersburg, Russia,
Sep 2010
196.
Gayaprasad Sinsinwar, Rahul Choudhary,
Aditi kajala, and Virendra Singh, `Test program
generation for simultaneous testing of multiple identical functional units`,
IEEE East-West Design and Test Symposium (EWDTS)
2010, St. Petersberg, Russia, Sep 2010
197.
Prasanth V.,
Virendra Singh, and Rubin Parekhji, `Robust detection
of soft errors using delayed capture methodology`, IEEE International Online
Testing Symposium (IOLTS) 2010,
Corfu, Greece, July 2010
198.
Pramod
Subramanyan, Virendra Singh, Kewal K. Saluja, and Erik Larsson, `Energy ffficient fault tolerance in chip multiprocessors using
critical value forwarding`, 40th IEEE International Conference on
Dependable Systems and Networks (DSN),
Chicago, IL, USA, June 2010.
199.
Abhishek A., Amanulla Khan, Virendra Singh, Kewal Saluja, and Adit Singh, `Test application time minimization for RAS
using basis optimization of column decoder`, IEEE International Symposium on
Circuits and Systems (ISCAS) 2010,
Paris, France, May 2010.
200.
Naveen
Choudhary, MS Gaur, Vijay Laxmi, and Virendra Singh, `Genetic algorithm based
topology generation for application specific network-on-chip`, IEEE
International Symposium on Circuits and Systems (ISCAS) 2010, Paris, France, May 2010.
201.
Raghavendra
Adiga, Arpit Gandhi, Virendra Singh, Kewal Saluja, and Adit
Singh, `Modified T-FF bases scan cell for RAS`, 15th IEEE European
Test Symposium (ETS) 2010, Prague,
Czech Rep., May 2010.
202.
Jaynarayan Tudu, Erik Larsson, Virendra Singh, and Hideo
Fujiwara, `Scan cell reordering to minimize peak power during test cycle: A
graph theoretic approach`, 15th IEEE European Test Symposium (ETS) 2010, Prague, Czech Rep., May
2010.
203.
Pramod
Subramanyan, Virendra Singh, Kewal K. Saluja, and Erik Larsson, `Power
efficient redundant execution for chip multiprocessors`, Great Lake Symposium
on VLSI (GLSVLSI) 2010, Providence,
Rhode Island, USA May 2010.
204.
Jaynarayan Tudu, Erik Larsson, Virendra Singh, and Hideo
Fujiwara, `Graph theoretic approach for scan cell reordering to minimize peak
shift power`, 20th ACM Great Lake Symposium on VLSI (GLSVLSI) 2010, Providence, Rhode
Island, USA May 2010
205.
Dimitar Nikolov, Erik Karlsson, Urban Ingelsson,
Virendra Singh, and Erik Larsson, `Mapping and scheduling of jobs in
homogeneous NoC-based MPSoC`, 10th Swedish
System-on-Chip Conference, Kolmarden, Sweden, May
2010
206.
Pramod
Subramanyam, Virendra Singh, Kewal Saluja, and Erik Larsson, `A low cost
redundant execution architectures for Chip multiprocessors`, Design Automation
and Test in Europe (DATE) 2010,
Dresden, Germany, March 2010.
207.
L. Suresh, N. Rameshan, A. Narayan, M. Zwolinski, M.S. Gaur, V. Laxmi,
and V. Singh, `EDA design flow acceleration by GP-GPU`, 2nd Workshop
on Designing for embedded parallel computing plateform:
Architectures, design tools, and applications (in conjunction with DATE 2010)
2010, Dresden, Germany, March 2010.
208.
Naveen
Choudhary, MS Gaur, Vijay Laxmi, and Virendra Singh, `Fast energy aware
application specific network-on-chip topology generator`, IEEE International
Advanced Computing Conference 2010, Patiala, India, Feb 2010.
209.
Dimitar
Nikolov, Urban Ingelsson, Virendra Singh, and Erik Larsson, `Estimating error
probability and its application for optimizing roll-back recovery with
checkpointing`, IEEE Symposium on Electronic Design, Test & Applications (DELTA) 2010, Ho Chi Minh , Vietnam, Jan
2010
210.
Dimitar
Nikolov, Urban Ingelsson, Virendra Singh, and Erik Larsson, `On-line techniques
to adjust and optimize checkpointing frequency`, IEEE International Workshop on
Reliability Aware System Design and Test (RASDAT)
2010, Bangalore, India, Jan 2010
211.
Raghavendra
Adiga, Arpit Gandhi, Virendra Singh, Kewal Saluja, Hideo Fujiwara, and Adit Singh, `On Minimization of Test Application Time for
RAS`, 23rd International Conference on VLSI Design (ICVD) 2010, Bangalore, Jan 2010.
212.
Suraj Sindia,
Virendra Singh, and Vishwani D. Agrawal, `Parametric Fault Diagnosis of
Nonlinear Analog Circuits using Polynomial Coefficients`, 23rd International
Conference on VLSI Design (ICVD)
2010, Bangalore, Jan 2010.
In 2009
213.
Naveen
Choudhary, MS Gaur, Vijay Laxmi, and Virendra Singh, `Cojoined Irregular
Topology and Routing Table Generation for Network-on-Chip`, IEEE INDICON 2009,
Gandhi Nagar, India, Dec 2009.
214.
Naveen
Choudhary, MS Gaur, Vijay Laxmi, and Virendra Singh, `Designing Application
Specific Irregular Topology for Network-on-Chip`, 17th International
Conference on Advanced Computing and Communications (ADCOM) 2009, Bangalore, Dec 2009.
215.
Jaynarayan Tudu, Erik Larsson, Virendra Singh, and Hideo
Fujiwara, `Scan Cells Reordering to Minimize Peak Power during Scan Testing of
SoC`, IEEE WRTLT 09, Hong Kong, Nov.
2009.
216.
Venkat Rajesh,
Erik Larsson, MS Gaur, and Virendra Singh, `An Even Odd DFD Technique for Scan
Chain Diagnosis`, IEEE WRTLT 09,
Hong Kong, Nov. 2009.
217.
Suraj Sindia,
Virendra Singh, and Vishwani Agrawal, `Multi-tone Testing of Linear and
Nonlinear Analog Circuits using Polynomial Coefficients`, IEEE Asian Test
Symposium (ATS) 2009, Taichung,
Taiwan, Nov 2009.
218.
Deepak K.G.,
Robinson Reyna, Virendra Singh, and Adit Singh,
`Leveraging Partial Enhanced Scan for Improved Observabilty
in Delay Fault Testing`, IEEE Asian Test Symposium (ATS) 2009, Taichung, Taiwan, Nov 2009.
219.
Suraj Sindia,
Virendra Singh, and Vishwani Agrawal, `V-Transform: An Enhanced Polynomial
Coefficient Based DC Test for Non-linear Analog Circuits`, IEEE East-West
Design and Test Symposium (EWDTS)
2009, Moscow, Russia, Sep 2009.
220.
Pramod
Subramanyan, Ram Rakesh Jangir, Jaynarayan Tudu, Erik
Larsson, and Virendra Singh, `Generation of Minimum Leakage Input Vectors with
Constrained NBTI Degradation`, IEEE East-West Design and Test Symposium (EWDTS) 2009, Moscow, Russia, Sep 2009.
221.
Viney Kumar,
Rahul Raj, and Virendra Singh, `FREP: A Soft-Error Resilient Pipelined RISC
Architecture`, IEEE East-West Design and Test Symposium (EWDTS) 2009, Moscow, Russia, Sep 2009.
222.
Jaynarayan Tudu, Erik Larsson, Virendra Singh, and Adit Singh, `Capture Power Reduction for Modular
System-on-Chip Test`, IEEE/VSI VLSI Design and Test Symposium (VDAT), Bangalore, India, July 2009.
223.
Suraj Sindia,
Virendra Singh, and Vishwani Agrawal, `Bounds on Defect Level and Fault
Coverage in Linear Analog Circuit Testing`, IEEE/VSI VLSI Design and Test
Symposium (VDAT), Bangalore, India,
July 2009.
224.
Pramod
Subramanyan, Virendra Singh, Kewal K. Saluja, and Erik Larsson, `Power
Efficient Redundant Execution for Chip Multiprocessor`, Workshop on Dependable
and Secure Nanocomputing (WDSN)
2009, Lisbon, Portugal, June 2009.
225.
Jaynarayan Tudu, Erik Larsson, Virendra Singh, and Vishwani D.
Agrawal, `On Minimization of Peak Power
during SoC Test`, IEEE European Test Symposium (ETS) 2009, Seville, Spain, May 2009.
226.
Suraj Sindia,
Virendra Singh, and Vishwani D. Agrawal, `Polynomial
Coefficient Based Multi-Tone Testing of Analog Circuits`, 18th
IEEE North Atlantic Test Workshop (NATW)
2009, New York, USA, May 2009.
227.
Reshma Jumani,
Niraj Jain, Virendra Singh, and Kewal K. Saluja, `DX-Compactor: Distributed X-Compaction for SoC Test`, ACM Annual
Great Lake Symposium on VLSI (GLSVLSI)
2009, Boston, USA, May 2009.
228.
Suraj Sindia,
Virendra Singh, and Vishwani Agrawal, `Coefficient-Based
Parametric Testing of Non-Linear Analog Circuits`, ACM Annual Great Lake
Symposium on VLSI (GLSVLSI) 2009,
Boston, USA, May 2009.
229.
Mikael Vayrynen, Virendra Singh, and Erik Larsson, `Fault-Tolerant Average Execution Time
Optimization for General Purpose Multi-Processor System-on-Chips`, Intl.
Conference on Design Automation and Test in Europe (DATE) 2009, Nice, France, Apr 2009.
230.
Vinay NS, Erik
Larsson, and Virendra Singh, `Thermal Aware Test Scheduling of Stacked
Multi-Chip Modules`, Workshop on 3D Integration (In conjunction with DATE
2009), Nice, France, Apr 2009.
Selected
Publications (Before
2008):
·
Virendra Singh, Michiko Inoue, Kewal K. Saluja, and
Hideo Fujiwara, `Testing Superscalar Processors in Functional Mode`, Proceedings
of the 15th International Conference on Field Programmable
Logic and Applications, Aug. 2005.
·
Virendra Singh, Michiko Inoue, Kewal K. Saluja, and
Hideo Fujiwara, `Instruction-Based Delay Fault Self-Testing of Pipelined
Processor Cores`, Proceedings of the IEEE International Symposium on
Circuits and Systems (ISCAS)
2005, Kobe, Japan, May 2005.
·
Virendra Singh, Michiko Inoue, Kewal K. Saluja, and
Hideo Fujiwara, `Instruction-Based Delay Fault Testing of Processor Cores`, Proceedings
of the International Conference on VLSI Design (VLSID) 2004, Mumbai, India Jan. 2004.
·
Virendra Singh, Michiko Inoue, Kewal K. Saluja, and
Hideo Fujiwara, `Software-Based Delay Fault Testing of Processor Cores`, Proceedings
of the IEEE 12th Asian Test Symposium (ATS) 2003, Xian, China, Nov. 2003.