Academics :

• B.E., Electronics and Instrumentation Engineering, SGSITS, Indore (2016-2020)
• M.Tech: (TA) Electronic Systems Design (EE5), IIT Bombay (2020- ongoing)

Research Interests: Digital VLSI Design, Procesor Design, Testing and Verification of VLSI circuits

Course Project:

• Design of 5-stage Pipelined RISC Processor (Processor Design – Spring 2021)
• HDL based approach for Texture Classification using Gabor Filters (VLSI Design Lab – Spring 2021)
• Design of Reset-Stabilized High Gain DC Differential Amplifier (Electronic Systems Design – Spring 2021)
• Design and Simulation of N-bit Brent Kung Adder
• Rail-to-rail two folded cascode stages Operational Amplifier (CMOS Analog VLSI Design – Autumn 2020)