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Angada B. Sachid
(Technology-Circuit Co-design using FinFETs for Sub-32nm
Technology) |
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Mayank Shrivastava
(I/O device optimization for sub 32nm node CMOS technology) |
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Venkatnarayan
Hariharan(Compact Model Development for FinFETs) |
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Sudhakar Mande
(Statistical Design of Integrated Circuits) |
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Hasanali G. Virani(Low Temperature CMOS Operation) |
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Kaushik Nayak
(Analytical Modeling of Nanoscale Transistors) |
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Piyush Dak
(Charge Trap Flash Memory) |
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Aradhana Gautam
(Sub 100nm CMOS Technology & Optimization) |
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Rohit V. Pandharipande
(Molecular Electronics) |
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Gooty Sukumar Reddy
(Devices sub 0.5V operation for low power applications) |
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Kshitij Auluck
(Simulator for Metal Nanodot memory under NAND operation) |
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Debarsi
(Flash Memory Simulation) |
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Nidhi Agrawal
(High Voltage Application of Novel devices in sub 22nm node Technology) |
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Anukool Rajoriya
(Super Steep Sub-threshold Nanoscale Devices) |
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System Adminstrator
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Amrut Kolhapure
M.Tech (Final Year) |
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Oves Badami M.Tech (Second
Year)
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Kaushik Nayak Senior Phd
|