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RÉSUME
Name : Sanjay S Pawar
Date of Birth : 1st March, 1970
Present Address
Institute of Technology for Women SNDT,
Juhu Road, Santacruz(w) Mumbai - 400 076, India.
Tel: 6606197
E-mail Address : sspawar@ieee.org
Home Page : http://members.xoom.com/sspawar
Educational Qualifications:-
| Sr.No | Examination | Institute/University | Year of Passing | Remark |
| 1. | M.Tech(Communication) | I.I.T. Mumbai | 1998 | 8.1(CPI) |
| 2. | B.E.(Electronics) | S.G.G.S, Nanded | 1991 | 70.42 % (Distinction) |
| 3 | H.S.C | Dayanand Science College, Latur,Aurangabad Board |
1987 | 85.33% (Distinction) |
| 4 | S.S.C | B.W.New English Medium School, Latur. Aurangabad Board |
1985 | 68.42 % ( First Div) |
Subjects/Courses Studied
| In this project work has been done to formulate the effect of EM interference on integrated circuits.Initial part of the work is limited for the CMOS devices. For this Spice modelling is done to verify the results obtained. In a digital system interference will cause two types of failures.The static failure which will be caused when interfering signal is more than certain threshold to produce a false level of the voltage.The other is dynamic failure. Tremendous increase in switching speed results in considering the importance of the timing issue during the logic system design. Lower interference levels causes the dynamic failures. This will change the propagation delay by significant amount, which will lead to violation of timing constraints.This occurs during the transition of the input pulse and when interference frequency is smaller or not too higher than maximum switching frequency of the incoming pulse. If the change in the propagation delay is within the delay margin then circuit performs well otherwise it will fail. That is the timing conditions are to be satisfied for the synchronous and asynchronous circuits for its proper functioning.Finally a complete model for the CMOS is formulated which will give the performance measure for the EM interference. |
Industrial Experiance:
Organization:- Desai Electronics
Duration :-August 1991 to August 1992
Nature of Job:- Involved in development of capacitor manufacturing equipments and development
Organization:- Bharati Vidyapeeth
Duration :- August 1992 to July 1996
Nature of work:- Worked as a lecturer and in the development of the Industrial Projects.
Organization:- IIT Bombay
Duration :-July 1992 to Jan 1998
Nature of work:- A asistant in computer lab of the Electrical Engineering Deprtment and seting and development of the INTEL lab in EE department.
Organization:- Bharati Vidyapeeth:-
Duration :- Jan 98 to Aug99
Nature of Work :- Assist Professor in electronics and Telecommunication. Department and development of the Industrial Application Projects
Organization :- Institute of Technology for Women, SNDT
Duration:- Aug 99 till date
Nature of Job :- Assist Prof in Electronics and Telecommunication department.
Development of the Project "Management Inforamtion System" for a Organization,
Texture segmentation and analysis.
Dept. of Electrical Engineering,
Indian Institute of Technology,
Bombay - 400 076, India.
Email :rmp@ee.iitb.ernet.in
Sanjaay S Pawar
ITW, SNDT Santacruz(w)
Wed March 1, 2000