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Juzer M. Vasi
Photo -Juzer M. Vasi
Contact Information
Room no: 205-A
Department of Electrical Engineering
Indian Institute of Technology Bombay
Powai, Mumbai 400076, India
Tel: +91-22-25767408 Fax: +91-22-25723707
Phone:+91-22-2576-7408
Email: vasi[AT]ee.iitb.ac.in
Homepage

Publications

journal papers
  1. C. Sandhya, A. Oak, N. Chattar, U. Ganguly, C. Olsen, S. M. Seutter, L. Date, R. Hung, J. Vasi and S. Mahapatra, "Study of P/E cycling enduranceinduced degradation in SANOS memories under NAND (FN/FN) operation", IEEE Trans. Electron Devices, vol. 57, pp. 1548 - 1558, 2010.
  2. V. Hariharan, J. Vasi and V. Ramgopal Rao, "An improvement to the numerical robustness of the surface potential approximation for double-gate MOSFETs", IEEE Transactions on Electron Devices, vol. 56, pp. 529, 2009.
  3. C. Sandhya, U. Ganguly, N. Chattar, C. Olsen, S. M. Seutter, L. Date, R. Hung, J. Vasi, and S. Mahapatra, "Effect of SiN on Performance and Reliability of Charge Trap Flash (CTF) Under Fowler Nordheim Tunneling Program/Erase Operation", Electron. Device Lett., vol. 30, pp. 171, 2009.
  4. V. Hariharan, J. Vasi and V. R. Rao, "Drain current model including velocity saturation for symmetric double-gate MOSFETs", IEEE Transactions on Electron Devices, vol. 55, 2008.
  5. P. Jain, J. Vasi and R. Lal, "SEU Reliability - Study of advanced deep sub-micron transistors", IEEE Trans. Device and Materials Reliability, vol. 5, 2005.
  6. S. N. Agarwal, A. Jha, D. Vinay Kumar, J. M. Vasi, M. B. Patil, S. C. Rustagi, "Look-up Table Approach for RF Circuit simulation Using a Novel Measurement Technique", IEEE Transactions on Electron Devices, vol. 52, pp. 973, 2005.
  7. A. S. Roy, J. Vasi, and M. B. Patil, "A new approach to model Non-Quasi-Static (NQS) effects in MOSFET’s Part I: Large-signal analysis", IEEE Trans. Electron Devices, vol. 51, 2004.
  8. K.N.Manjularani, V. R. Rao and J. Vasi, "Stress voltage polarity dependence of JVD Si3N4 MNSFET degradation", IEEE Trans. Device and Materials Reliability, vol. 4, 2004.
  9. K.N.Manjularani, V. R. Rao and J. Vasi, "A New Method to Characterize Border Traps in Sub-Micron Transistors using Hysteresis in the Drain Current", IEEE Transactions on Electron Devices, vol. 50, pp. 973, 2003.
  10. Najeeb-ud-din, Mohan V. Dunga, Aatish Kumar, J.Vasi, V.Ramgopal Rao, Baohong Cheng, J.C.S.Woo, "Analysis of Floating Body Effects in Thin Film Conventional and Single Pocket SOI MOSFETs using the GIDL Current Technique", IEEE Electron Device Letters, vol. 23, 2002.
  11. S. Mahapatra, V. Ramgopal Rao, B. Cheng, M. Khare, C. D. Parikh, J. C. S. Woo and J. Vasi, "Performance and Hot-Carrier Reliability of 100 nm Channel Length Jet Vapor Deposited Si3N4 MNSFETs", IEEE Trans. on Electron Devices, vol. 48, pp. 679, 2001.
  12. S. Mahapatra, V.Ramgopal Rao, J. Vasi, B.Cheng, J.C.S.Woo, "A Study of Hot-Carrier Induced Interface-Trap Profiles in Lateral Asymmetric Channel MOSFETs Using a Novel Charge Pumping Technique", Solid-State Electronics, vol. 45, pp. 1717, 2001.
  13. S. Mahapatra, C. D. Parikh, V. Ramgopal Rao, C. R. Vishwanathan and J. Vasi, "A comprehensive study of hot-carrier induced interface and oxide trap distributions in MOSFETs using a novel charge pumping technique", IEEE Trans. Electron Devices, vol. 47, pp. 171, 2000.
  14. Mahapatra, C. D. Parikh and J. Vasi, "A new ‘multifrequency’ charge pumping technique to profile hot-carrier induced interface-state density in nMOSFETs", IEEE Trans. Electron Devices, vol. 46, pp. 960, 1999.
  15. S. Subbaraman, D. K. Sharma, J. Vasi, and A. Das , "A monte carlo approach for incorporation of memory effect in switched gate bias experiments", Journal of Applied Physics, vol. 83, pp. 3419–3422, Mar. 1998.
  16. V. Ramgopal Rao, I. Eisele, R.M. Patrikar, D.K. Sharma, J. Vasi and T. Grabolla , "High-field stressing of lpcvd gate oxides", Electron Device Letters, IEEE, vol. 18, no. 3, pp. 84-86, Mar. 1997.
  17. V. R. Rao, W. Hansch, H. Baumgartner, I. Eisele, D. K. Sharma, T. Grabolla and J. Vasi , "Charge trapping behaviour in deposited and grown thin MOS gate dielectrics", Thin Solid Films, vol. 296, pp. 37–40, Mar. 1997.
  18. P.V.S. Subrahmanyam, A. Prabhakar and J. Vasi, "High-field stressing effects on the split N2O grown thin gate dielectrics by rapid thermal processing", IEEE Trans. Electron Devices, vol. 44, pp. 505, 1997.
  19. V. Ramgopal Rao, D.K. Sharma and J. Vasi , "Neutral electron trap generation under irradiation in reoxidized nitrided gate dielectrics", Electron Devices, IEEE Transactions, vol. 43, no. 9, pp. 1467–1470, Sep. 1996.
  20. V. Ramgopal Rao, D.K. Sharma and J. Vasi, "Neutral electron trap generation under irradiation for RNO gate dielectrics", IEEE Trans. Electron Devices, vol. 43, pp. 1467, 1996.
  21. R.M.Patrikar, R.Lal and J.Vasi, "Interface-state generation due to high-field stressing in MOS oxides", Solid-St. Electron., vol. 38, pp. 477, 1995.
  22. V.Vasudevan and J.Vasi, "A two-dimensional numerical simulation of oxide charge build up in MOS transistors due to radiation", IEEE Trans. Electron Devices, vol. 41, pp. 383, 1994.
  23. A. Phanse, D. Sharma, A. Mallik and J. Vasi , "Carrier mobility degra- dation in metal-oxide-semiconductor field-effect transistors due to oxide charge", Journal of Applied Physics, vol. 74, pp. 757–759, Jul. 1993.
  24. R.M.Patrikar, R.Lal and J.Vasi, "Net positive charge buildup in various MOS insulators due to high-field stressing", IEEE Electron Device Letters, vol. 14, pp. 533, 1993.
  25. S.S.Moharir, A.N.Chandorkar and J.Vasi, "An interface reaction mechanism for the dry oxidation of silicon", J. Appl. Phys., vol. 65, pp. 3958, 1989.
  26. R.Lal and J.Vasi, "Profiling generation lifetime in a MOS capacitor using a multistep constant capacitance technique", Solid-State Electronics, vol. 30, pp. 801, 1987.
  27. C.D.Parikh and J.Vasi, "Modelling of a depletion-mode MOSFET", Solid-State Electronics, vol. 30, pp. 699, 1987.
  28. K.Ramesh, A.N.Chandorkar and J.Vasi, "Study of electron traps in silicon dioxide due to mobile sodium ions at the Si-SiO2 interface", J.I.E.T.E., vol. 33, pp. 38, 1987.
  29. S.K.Madan, B.Bhaumik and J.Vasi, "Experimental observation of avalanche multiplication in charge-coupled devices", EEE Trans. Electron Devices, vol. ED-30, pp. 694, 1983.
  30. A.B.Bhattacharyya, L.Manchanda and J.Vasi, "The effect of trichloroethylene molar concentration on the storage time of MOS capacitors", Ind. J. Pure and Appl. Phy, vol. 21, pp. 1, 1983.
  31. P.Tiwari, B.Bhaumik and J.Vasi, "Rapid measurement of lifetime using a ramped MOS capacitor transient", Solid-St. Electron., vol. 26, no. 695, 1983.
  32. A.B.Bhattacharyya, L.Manchanda and J.Vasi, "Electron traps in SiO2 grown in the presence of trichloroethylene", J. Electrochem. Soc., vol. 129, pp. 2772, 1982.
  33. S.K.Madan, B.Mathur and J.Vasi, "Feed forward due to barrier modulation in charge-coupled devices", IEEE Trans. Electron Devices, vol. ED-29, pp. 1269, 1982.
  34. L.Manchanda, J.Vasi and A.B.Bhattacharyya, "The nature of intrinsic hole traps in thermal silicon dioxide", Journal of Applied Physics, vol. 52, pp. 4690, 1982.
  35. J.Vasi, K.L.Chopra and T.C.Goel, eds., "Physics of semiconductor-insulator interfaces in Vacuum-Surfaces-Thin Films", Vanity Books, New Delhi, 1981.
  36. L.Manchanda, J.Vasi and A.B.Bhattacharyya, "Hole traps in thermal silicon dioxide introduced by chlorine", Applied Physics Letters, vol. 37, pp. 744, 1980.
  37. L.Manchanda, J.Vasi and A.B.Bhattacharyya, "The effect of high temperature annealing on the spatial variation of lifetime near the Si-SiO2 interface", Solid-State Electronics, vol. 23, pp. 1015, 1980.
  38. K.S.Chari, B.Mathur and J.Vasi, "A novel double-dielectric two-phase CCD with overlapping gates", Microelectronics Journal, vol. 9, pp. 24, 1979.
  39. L.Manchanda, J.Vasi and A.B.Bhattacharyya, "Determination of surface-state density from pulsed MOS capacitor transients", Solid-St. Electron., vol. 22, pp. 29, 1979.
  40. A.B.Bhattacharyya, R.K.Nahar, D.Nagchoudhuri and J.Vasi, "Electrical properties of CdS-SiO2-Si structures", J.I.E.T.E., vol. 50, pp. 390, 1979.
  41. S.C.Dutta Roy, A.B.Bhattacharyya, J.Vasi, V.G.Das, L.Shankar and N.Kapur, "Signal processing applications of charge-coupled devices", J.I.E.T.E., vol. 24, pp. 400, 1978.
  42. J.Vasi and C.R.Westgate, "Recombination oscillations in double-injection devices", Solid-St. Electron., vol. 17, pp. 513, 1974.
  43. J.Vasi and C.R.Westgate, "Double injection into insulators for non-planar geometry", Solid-St. Electron., vol. 16, pp. 277, 1973.

conference papers/book chapters
  1. M. N. Rao, D. K. R. Rai, C. S. Solanki and J. Vasi, "Optical bandgap tuning of ICPCVD made silicon nanocrystals for for next generation photovoltaics" in 38th IEEE Photovoltaic Specialists Conference, Austin, USA 2012.
  2. C. S. Solaki, B. G. Fernandes, B. M. Arora, P. Sharma, V. Agarwal, M. B. Patil, J. Vasi, D. B. Phatak, M. Atrey, K. Moudgalya and K. Bijlani, "Teach a 1000 Teachers: A methodology for the rapid ramp-up of photovoltaics manpower required for India’s national solar mission" in 38th IEEE Photovoltaic Specialists Conference, Austin, USA 2012.
  3. M. N. Rao, H. K. Singh, C. S. Solanki and J. Vasi, "Structural properties of ICPCVD fabricated SiO2/SiOx superlattice for use in beyond Shockley-Queissar limit solar cells" in 27th European Photovoltaic Solar Energy Conference (EUPVSEC), Frankfurt, Germany 2012.
  4. J. Vasi, "Photovoltaics for Green Technologies" in 6th National INAE Symposium on Frontiers of Engineering, Hyderabad, India 2011.
  5. Sandhya C., U. Ganguly, K.K. Singh, P.K. Singh, C. Olsen, S. M. Seutter, R. Hung, G. Conti, K. Ahmed, N. Krishna, J. Vasi and S. Mahapatra, "Nitride Engineering and the effect of interfaces on charge trap flash performance and reliability" in International Reliability Physics Symposium (IRPS) 2008.
  6. A. Nainani, S. Palit, P. K. Singh, U. Ganguly, N. Krishna, J. Vasi and S. Mahapatra, "Development of a 3D simulator for metal nanocrystal flash memories under NAND operation" in International Electron Devices Meeting (IEDM) 2007.
  7. P. Jain, D. V. Kumar, J. Vasi and M. B. Patil, "Evaluation of non-quasi-static effects during SEU in deep submicron MOS devices and circuits" in Proceedings of the 19th International Conference on VLSI Design (VLSI’06) 2006.
  8. P. Bharath Kumar, Ravinder Sharma, Pradeep R. Nair, Deleep R. Nair, S. Kamohara, S. Mahapatra, and J. Vasi, "Mechanism of Drain Disturb in SONOS Flash EEPROMs" in International Reliability Physics Symposium 2005.
  9. A. Jha, J. Vasi, S. C. Rustagi and M. B. Patil, "A novel method to obtain 3-port network parameters for a MOSFET from 2-port measurements" in International Conference on Microelectronic Test Structures, Hyogo, Japan 2004.
  10. Single-event-induced barrier lowering in deep sub-micron CMOS devices and circuits, "P. Jain, J. Vasi and R. Lal" in 11th International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA 2004), Taiwan 2004.
  11. K. N. ManjulaRani, V. Ramgopal Rao and J. Vasi, "Characterization of high-field stress-induced border traps in JVD Si3N4 transistors by drain current transient and 1/f methods" in 34th IEEE Semiconductor Interface Specialists Conference (SISC 2003), Washington, DC 2003.
  12. K. N. ManjulaRani, V. Ramgopal Rao and J. Vasi, "Reliability of ultra-thin JVD silicon nitride MNSFETs under high-field stressing" in 10th International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA 2003), Singapore 2003.
  13. Najeeb-ud-Din, Aatish Kumar, Mohan V.Dunga, V.Ramgopal Rao, J.Vasi, "Suppression of Parasitic BJT Action in Single Pocket Thin Film Deep Sub-micron SOI MOSFETs" in 2002 MRS Spring Meeting, San Francisco, California 2002.
  14. K. N. ManjulaRani, V. Ramgopal Rao and J. Vasi, "Degradation Study of Ultra-Thin JVD Silicon Nitride MNSFET" in 2002 MRS Spring Meeting, San Francisco, California 2002.
  15. A. Khamesra, R. Lal , J. Vasi, A. Kumar K. P. and J. K. O. Sin, "Device degradation of n-channel poly-Si TFT’s due to high-field, hot-carrier and radiation stressing" in 8th International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA 2001), Singapore 2001.
  16. Najeeb-ud-Din, M. V. Dunga, Aatish Kumar, V. Ramgopal Rao and J. Vasi, "Characterization of Lateral Asymmetric Channel (LAC) Thin Film SOI MOSFETs" in Sixth International Conference on Solid-State and Integrated-Circuit Technology (ICSICT 2001), Shanghai, China 2001.
  17. K. N. ManjulaRani, V. Ramgopal Rao and J. Vasi, "Border trap characterization in ultra-thin JVD nitride capacitors" in 32nd IEEE Semiconductor Interface Specialists Conference (SISC 2001), Washington, DC 2001.
  18. D. R. Nair, M. B. Patil and J. Vasi, "Extraction of effective mass of carriers in Si3N4 by accurate modeling of gate tunneling current" in 32nd IEEE Semiconductor Interface Specialists Conference (SISC 2001), Washington, DC 2001.
  19. K. G. Anil, S. Mahapatra, I. Eisele, V. R. Rao and J. Vasi, "Drain bias dependence of gate oxide reliability in conventional and asymmetrical channel MOSFETs" in 30th European Solid-State Device Research Conference (ESSDERC 2000), Cork, Ireland, pp. 132-135, Sep. 2000.
  20. V. Ramgopal Rao, S. Mahapatra,, J.Vasi, K. G. Anil, C. Fink, W. Hansch and I. Eisele, "Hot-carrier performance of 60 nm channel length delta-doped vertical MOSFETs with high-pressure grown oxide as a gate dielectric" in 31st IEEE Semiconductor Interface Specialists Conference (SISC 2000), San Diego, California 2000.
  21. A.Topkar, S. Lodha and J. Vasi, "Ionizing radiation induced degradation of SiGe HBTs" in in Proceedings of the 10th Intl. Workshop on Physics of Semiconductor Devices, New Delhi, India, pp. 659-662, Dec. 1999.
  22. S. Mahapatra, V. Ramgopal Rao, K. N. ManjulaRani, C. D. Parikh, J. Vasi, B. Cheng, M. Khare and J. C. S. Woo, "100 nm channel length MNSFETs using a Jet Vapor Deposited ultra-thin silicon nitride gate dielectric" in Int. Symposium on VLSI Technology, Kyoto, Japan 1999.
  23. S. Mahapatra, V. Ramgopal Rao, C. D. Parikh, J. Vasi, B. Cheng and J. C. S. Woo, "A study of 100 nm channel length asymmetric MOSFET by using charge pumping" in Int. Conf. on Insulating Films on Semiconductors (INFOS ‘99), Erlangen, Germany 1999.
  24. S. Mahaptra, V. Ramgopal Rao, C. D. Parikh, J. Vasi, B. Cheng, M. Khare and J. C. S. Woo, "Hot-carrier induced interface-state degradation in JVD SiN MNSFETs as studied by a novel charge pumping technique" in 29th European Solid-State Device Research Conference (ESSDERC 99), Leuven, Belgium 1999.
  25. A. Topkar, S. Lodha, A. T. Mahfooz, R. Lal, J. Vasi and L. Nanver, "Ionizing radiation induced degradation of SiGe HBTs" in 10th Int. Workshop on Physics of SemiconductorDevices, New Delhi 1999.

Miscellaneous

Technical and Professional Contributions
  1. Co-Principal Investigator, Centre of Excellence in Nanoelectronics (CEN), 2006-2011
  2. Principal Investigator, National Centre for Photovoltaic Research & Education (NCPRE), 2010-2012
  3. Editor, IEEE Transactions on Electron Devices, 1996-2003
  4. Over 140 papers published in journals and presented at international conferences
  5. Co-Principal Investigator, Indian Nanoelectronics Users Programme (INUP), 2008-2012
  6. Investigator/co-investigator in funded projects from microelectronics industries like Motorola (USA), Siemens AG (Germany), National Semiconductor Corp. (USA), Renesas (Japan), Indian Telephone Industries, Bharat Electronics Ltd. (India), Semiconductor Complex Ltd. (India), etc.
  7. Member, Working Group on Technology of the National Microelectronics Council, Govt. of India, 1988-1994
  8. Member, Scientific Advisory Committee to the Cabinet (SAC-C), 2008-present
  9. Member, Solar Energy Research Advisory Council, Ministry of New and Renewable Energy, Govt. of India, 2011-present
  10. Member, Program Advisory Committee on Electrical, Electronics and Computer Engineering, Department of Science & Technology, Govt. of India, 1998-2003

Honours
  1. Elected to The Johns Hopkins Society of Scholars, 1993
  2. Fellow, IETE
  3. Fellow, INAE
  4. Fellow, IEEE

Professional Society Activities
  1. Chairman, IEEE Asia-Pacific Regions/Chapters Subcommittee, 2005-2006
  2. Guest Editor, Journal of IETE Special Issue on Microelectronics, 1990
  3. Chairman, IEEE Bombay Section, 2001-2002
  4. Founding Chairman, IEEE APS/EDS Bombay Chapter, 1999-2000
  5. Editor, IEEE Transactions on Electron Devices, 1996-2003
  6. Distinguished Lecturer of the IEEE Electron Devices Society, 2001-2005