faculty photo
Anil Kottantharayil
Address:
Department of Electrical Engineering
IIT Bombay, Powai
Mumbai 400 076, India
  • Phone (O): +91-22-2576-7438
  • Phone (R): +91-22-2576-8438
  • E-Mail: anilkg[AT]ee.iitb.ac.in
  • Homepage

List of Publications

Journal Papers

  1. Prabir Kanti Basu, KP Sreejith, Tarun Singh Yadav, Anil Kottanthariyil, and Ashok Kumar Sharma, "Novel low-cost alkaline texturing process for diamond-wire-sawn industrial monocrystalline silicon wafers", Solar Energy Materials and Solar Cells, vol. 185, pp. 406-414, Oct. 2018. [DOI]
  2. Tarun Singh Yadav, Ashok Kumar Sharma, Anil Kottantharayil, and Prabir Kanti Basu, "Low-cost and low-temperature chemical oxide passivation process for large area single crystalline silicon solar cells", Solar Energy, vol. 169, pp. 270-276, Jul. 2018. [DOI]
  3. Poonam Jangid, Dawuth Pathan, and Anil Kottantharayil, "Graphene nanoribbon transistors with high I ON /I OFF ratio and mobility", Carbon, vol. 132, pp. 65-70, Jun. 2018. [DOI]
  4. Abhishek Misra, Amritha Janardhan, Manali Khare, Hemen Kalita, and Anil Kottantharayil, "Reduced Multilayer Graphene Oxide Floating Gate Flash Memory with Large Memory Window and Robust Retention Characteristics", IEEE Electron Device Letters, vol. 34, no. 9, pp. 1136-1138, Sep. 2013.
  5. Sandeep S. S. and Anil Kottantharayil, "Plasma Grown Oxy-nitride Films for Silicon Surface Passivation", IEEE Electron Device Letters, vol. 34, no. 7, pp. 918 - 920, Jul. 2013.
  6. Meenakshi Bhaisare, Abhishek Misra, and Anil Kottantharayil, "Aluminum Oxide Deposited by Pulsed-DC Reactive Sputtering for Crystalline Silicon Surface Passivation", IEEE Journal of Photovoltaics, vol. 3, no. 3, pp. 930-935, Jul. 2013.
  7. Fischer, I.A., Bakibillah, A.S.M., Golve, M., Hahnel, D., Isemann, H., Kottantharayil, A., Oehme, M., and Schulze, J., "Silicon Tunneling Field-Effect Transistors With Tunneling in Line With the Gate Field", IEEE Electron Device Letters, vol. 34, no. 2, pp. 154-156, Feb. 2013.
  8. Kousik Midya, Subhabrata Dhar, and Anil Kottantharayil, "Trap characterization of silicon nitride thin films by a modified trap spectroscopy technique", Journal of Applied Physics, 2013.
  9. Meenakshi Bhaisare, Abhishek Misra, Mayur Waikar and Anil Kottantharayil, "High quality Al2O3 dielectric films deposited by pulsed- DC reactive sputtering technique for high-k applications", Nanoscience and Nanotechnology Letters, vol. 4, no. 6, pp. 645-650, Jun. 2012.
  10. Suresh Gundapaneni, Mohit Bajaj, Rajan K. Pandey, Kota V. R. M. Murali, Swaroop Ganguly and Anil Kottantharayil, "Effect of Band-to-Band Tunneling on Junctionless Transistors", IEEE Transactions on Electron Devices, vol. 59, no. 4, pp. 1023 - 1029, Apr. 2012.
  11. Abhishek Misra, Mayur Waikar, Amit Gour, Hemen Kalita, Manali Khare, Mohammed Aslam and Anil Kottantharayil, "Work function Tuning and Improved Gate Dielectric Reliability with Multilayer Graphene as a Gate Electrode for Metal Oxide Semiconductor Field Effect Device Applications", Applied Physics Letters, vol. 100, no. 23, pp. 233506, 2012.
  12. Suresh Gundapaneni, Swaroop Ganguly and Anil Kottantharayil, "Enhanced electrostatic integrity of short channel junctionless transistor with high-k spacers", IEEE Electron Device Letters, vol. 32, no. 10, pp. 1325-1327, Oct. 2011.
  13. Hasanali G. Virani, Suresh Gundapaneni and Anil Kottantharayil, "Double Dielectric Spacer for the Enhancement of Silicon p-Channel Tunnel FET Performance", Japanese Journal of Applied Physics, vol. 50, pp. 04DC04, Apr. 2011.
  14. Suresh Gundapaneni, Swaroop Ganguly and Anil Kottantharayil, "Bulk Planar Junction-Less Transistor (BPJLT): An attractive device alternative for scaling", IEEE Electron Device Letters, vol. 32, no. 3, pp. 261-263, Mar. 2011.
  15. Hasanali G. Virani, Adari Rama Bhadra Rao and Anil Kottantharayil, "Dual-k Spacer Device Architecture for the Improvement of Performance of Silicon n-Channel Tunnel FETs", IEEE Transactions on Electron Devices, vol. 57, no. 10, pp. 2410-2417, Oct. 2010.
  16. Maheshwari, N., Kottantharayil, A., Kumar, M., Mukherji, S, "Long term hydrophilic coating on poly(dimethylsiloxane) substrates for microfluidic applications", Applied Surface Science, vol. 257, no. 2, pp. 451-452, 2010.
  17. Hasanali G. Virani, Rama Bhadra Rao and Anil Kottantharayil, "Investigation of Novel Si/SiGe Hetero Structures and Gate Induced Source Tunneling for Improvement of P-channel Tunnel FETs", Japanese Journal of Applied Physics, vol. 49, no. 12, pp. 04DC12, 2010.
  18. Walawalkar, M.G., Kottantharayil, A., Rao, V.R, "Chemical Vapor Deposition Precursors for High Dielectric Oxides: Zirconium and Hafnium Oxide", Synthesis and Reactivity in Inorganic, Metal-Organic and Nano-Metal Chemistry, vol. 39, no. 6, pp. 331-340, Jun. 2009.
  19. Thakker, R.A., Patil, M.B., Anil, K.G, "Parameter extraction for PSP MOSFET model using hierarchical particle swarm optimization", Engineering Applications of Artificial Intelligence, vol. 22, no. 2, pp. 317-328, 2009.
  20. Iyengar, V.V., Kottantharayil, A., Tranjan, F.M., Jurczak, M., De Meyer, K., "Extraction of the top and sidewall mobility in FinFETs and the impact of fin-patterning processes and gate dielectrics on mobility", IEEE Transactions on Electron Devices, vol. 54, no. 5, pp. 1177-1184, May 2007.
  21. Ferain, I., Pantisano, L., Kottantharayil, A., Petry, J., Trojman, L., Collaert, N., Jurczak, M., De Meyer, K., "Reduction of the anomalous VT behavior in MOSFETs with high-k/metal gate stacks", Microelectronic Engineering, vol. 84, no. 9-10, pp. 1882-1885, 2007.
  22. Kittl, J.A., Pawlak, M.A., Lauwers, A., Demeurisse, C., Hoffmann, T., Veloso, A., Anil, K.G., Kubicek, S., Niwa, M., van Dal, M.J.H., Richard, O., Jurczak, M., Vrancken, C., Chiarella, T., Brus, S., Maex, K., Biesemans, S., "Phase effects and short gate length device implementation of Ni fully silicided (FUSI) gates", Microelectronic Engineering, vol. 83, no. 11-12, pp. 2117-2121, Nov. 2006.
  23. Dixit, A., Anil, K.G., Collaert, N., Zimmerman, P., Jurczak, M., De Meyer, K., "Minimization of MuGFET source/drain resistance using wrap-around NiSi-HDD contacts", Solid-State Electronics, vol. 50, no. 7-8, pp. 1466-1471, Jul. 2006.
  24. Singanamalla, R., Yu, H.Y., Pourtois, G., Ferain, I., Anil, K.G., Kubicek, S., Hoffmann, T.Y., Jurczak, M., Biesemans, S., De Meyer, K, "On the impact of TiN film thickness variations on the effective work function of poly-Si/TiN/SiO2 and Poly-Si/TiN/HfSiON gate stacks", IEEE Electron Device Letters, vol. 27, no. 5, pp. 332-334, May 2006.
  25. Dixit, A., Anil, K.G., Rooyackers, R., Leys, F., Kaiser, M., Collaert, N., De Meyer, K., Jurczak, M., Biesemans, S., "Minimization of specific contact resistance in multiple gate NFETs by selective epitaxial growth of Si in the HDD regions", Solid-State Electronics, vol. 50, no. 4, pp. 587-593, Apr. 2006.
  26. Pawlak, M.A., Lauwers, A., Janssens, T., Anil, K.G., Opsomer, K., Maex, K., Vantomme, A., Kittl, J.A., "Modulation of the workfunction of Ni fully silicided gates by doping: Dielectric and silicide phase effects", IEEE Electron Device Letters, vol. 27, no. 2, pp. 99-101, Feb. 2006.
  27. Kittl, J.A., Pawlak, M.A., Lauwers, A., Demeurisse, C., Opsomer, K., Anil, K.G., Vrancken, C., van Dal, M.J.H., Veloso, A., Kubicek, S., Absil, P., Maex, K., Biesemans, S., "Work function of Ni silicide phases on HfSiON and SiO2: NiSi, Ni2Si, Ni31Si12, and Ni3Si fully silicided gates", IEEE Electron Device Letters, vol. 27, no. 1, pp. 34-36, Jan. 2006.
  28. Janssens, T., Pawlak, M.A., Kittl, J.A., Fouchier, M., Lauwers, A., Kottantharayil, A., Vandervorst, W., "Dopant profiling in Nix Si1-X gates with secondary-ion-mass spectroscopy", Journal of Vacuum Science and Technology B, vol. 24, no. 1, pp. 399-403, Jan. 2006.
  29. Collaert, N., De Keersgieter, A., Anil, K.G., Rooyackers, R., Eneman, G., Goodwin, M., Eyckens, B., Sleeckx, E., de Marneffe, J.-F., De Meyer, K., Absil, P., Jurczak, M., Biesemans, S., "Performance improvement of tall triple gate devices with strained SiN layers", IEEE Electron Device Letters, vol. 26, no. 11, pp. 820-822, Nov. 2005.
  30. Dixit, A., Kottantharayil, A., Collaert, N., Goodwin, M., Jurczak, M., De Meyer, K., "Analysis of the parasitic S/D resistance in multiple-gate FETs", IEEE Transactions on Electron Devices, vol. 56, no. 2, pp. 1132-1140, Jun. 2005.
  31. Collaert, N., Dixit, A., Anil, K.G., Rooyackers, R., Veloso, A., De Meyer, K., "Shift and ratio method revisited: Extraction of the fin width in multi-gate devices", Solid-State Electronics, vol. 49, no. 5, pp. 763-768, May 2005.
  32. Collaert, N., Dixit, A., Goodwin, M., Anil, K.G., Rooyackers, R., Degroote, B., Leunissen, L.H.A., Veloso, A., Jonckheere, R., De Meyer, K., Jurczak, M., Biesemans, S., "A functional 41-stage ring oscillator using scaled FinFET devices with 25-nm gate lengths and 10-nm fin widths applicable for the 45-nm CMOS node", IEEE Electron Device Letters, vol. 25, no. 8, pp. 568-570, Aug. 2004.
  33. Anil, K.G., Mahapatra, S., Eisele, I., "A detailed experimental investigation of impact ionization in n-channel metal-oxide-semiconductor field-effect-transistors at very low drain voltages", Solid-State Electronics, vol. 47, no. 6, pp. 995-1001, Jun. 2003.
  34. Anil, K.G., Mahapatra, S., Eisele, I, "Electron-electron interaction signature peak in the substrate current versus gate voltage characteristics of n-channel silicon MOSFETs", IEEE Transactions on Electron Devices,, vol. 49, no. 7, pp. 1283-1288, Jul. 2002.
  35. Fink, C., Anil, K.G., Geiger, H., Hansch, W., Kaesen, F., Schulze, J., Sulima, T., Eisele, "Enhancement of device performance in vertical sub-100 nm MOS devices due to local channel doping", Solid-State Electronics, vol. 46, no. 3, pp. 387-391, Mar. 2002.
  36. Anil, K.G., Mahapatra, S., Eisele, "Experimental verification of the nature of the high energy tail in the electron energy distribution in n-channel MOSFETs", IEEE Electron Device Letters, vol. 22, no. 10, pp. 478-480, Oct. 2001.
  37. K. G. Anil, S. Mahapatra, V. Ramgopal Rao and I. Eisele, "Comparison of Sub- Bandgap Impact Ionization in Deep-Sub-Micron Conventional and Lateral Asymmetrical Channel nMOSFETs", Japanese Journal of Applied Physics, vol. 40, no. 4B, pp. 2621-2626, Apr. 2001.
  38. Anil, K.G., Eisele, I., Mahapatra, S, "Observation of double peak in the substrate current versus gate voltage characteristics of n-channel metal-oxide-semiconductor field effect transistors", Applied Physics Letters, vol. 78, no. 15, pp. 2238-2240, 2001.
  39. Stadler, A., Sulima, T., Schulze, J., Fink, C., Kottantharayil, A., Hansch, W., Baumgärtner, H., Eisele, I., Lerch, W, "Dopant diffusion during rapid thermal oxidation", Solid-State Electronics, vol. 44, no. 5, pp. 831–835, May 2000.
  40. Fink, C., Anil, K.G., Geiger, H., Hansch, W., Schulze, J., Sulima, T., Eisele, I. , "Optimization of breakdown behaviour and short channel effects in MBE-grown vertical MOS-devices with local channel doping", Thin Solid Films, vol. 369, no. 1, pp. 383-386, Jan. 2000.
  41. Fink, C., Anil, K.G., Hansch, W., Sedlmaier, S., Schulze, J., Eisele, , "MBE-grown vertical power-MOSFETs with 100-nm channel length", Thin Solid Films, vol. 380, no. 1-2, pp. 207-210, 2000.
  42. Kaesen, F., Fink, C., Anil, K.G., Hansch, W., Doll, T., Grabolla, T., Schreiber, H., Eisele, "Optimization of the channel doping profile of vertical sub-100 nm MOSFETs", Thin Solid Films, vol. 336 , no. 1-2, pp. 309–312, Dec. 1998.

Conference Papers / Book Chapters

  1. A. K. Sharma, Manoj K. Ramanathi, Binny Nair, Tarun S. Yadav, Prabir K. Basu, Anil Kottantharayil, K. L. Narasimhan, and B. M. Arora, "Photoluminescence Imaging of Silicon Wafers & Solar Cells for Process, Device Development & Diagnostics" in 19th International Workshop on Physics of Semiconductor Devices (IWPSD), Dec. 2017.
  2. Tarun S. Yadav, Sandeep K., Ashok K. Sharma, Pradeep P., K. L. Narasimhan, B. M. Arora, Anil Kottantharayil, and Prabir K. Basu, "Cell efficiency enhancement in industrial monocrystalline silicon solar cells using new low-cost chemical passivation process" in 19th International Workshop on Physics of Semiconductor Devices (IWPSD), Best Poster Award, Dec. 2017.
  3. Tarun Singh Yadav, Sandeep Kumbhar, Ashok Kumar Sharma, Spandana B, K L Narasimhan, B M Arora, Anil Kottantharayil, and Prabir K. Basu, "A New Low-Cost and Low-Temperature Chemical Passivation Process for Large Area Industrial Single Crystalline Silicon Wafers" in IEEE 44th PVSC, Dec. 2017.
  4. Prabir K. Basu, Sandeep Kumbhar, Ashok K. Sharma, Pradeep Padmanabhan, Tarun S. Yadav, K. L. Narasimhan, B. M. Arora, and Anil Kottantharayil, "20.3% effective efficiency monocrystalline silicon solar cells using low-cost processing with laboratory fabrication tools" in 19th International Workshop on Physics of Semiconductor Devices (IWPSD), Dec. 2017.
  5. Sandeep S. Saseendran, Mehul C. Raval, Balraj A., Sandeep Kumbhar, Tarun S. Yadav, Pradeep P., S. Saravanan, and Anil Kottantharayil, "Approach of low-temperature oxidation for surface passivation and Ni/Cu metallization in crystalline silicon solar cells" in SNEC 10th International Photovoltaic Power Generation Conference, Shanghai, China, Dec. 2016.
  6. Ashwini S. Gajarushi, Dawuth Pathan, Tejas R. Naik, Mrinalini Walawalkar, M. Ravikanth, Anil Kottantharayil, V. Ramgopal Rao, "Porphyrin Induced Changes in Charge Transport of Graphene FET" in Proceedings of the 16th International Conference on Nanotechnology Sendai, Japan, August 22-25, 2016, IEEE, pp.4, Aug. 2016.
  7. Sandeep S. S., Tarun S. Yadav, Mehul C. Raval, A. Balraj, Sandeep K., Anzar G., S. Saravanan, and Anil Kottantharayil, "Low-temperature oxidation for emitter surface passivation in crystalline silicon solar cells" in 18th International Workshop on Physics of Semiconductor Devices (IWPSD), Dec. 2015.
  8. Fischer, I.A.; Hahnel, D. ; Isemann, H. ; Kottantharayil, A. ; Murali, G. ; Oehme, M. ; Schulze, J, "Si Tunneling Field Effect Transistor with Tunnelling In-Line with the Gate Field" in International Silicon-Germanium Technology and Device Meeting (ISTDM), Berkeley, USA, Dec. 2012.
  9. Kousik Midya, Abhishek Sharma, Anil Kottantharayil, Subhabrata Dhar, "RF sputtered ITO thin film with improved optical property" in MRS Spring Meeting 2012, San Francisco, USA. MRS ONline Proceedings Library, Dec. 2012.
  10. Sandeep S. S., Ketan Warikoo, Anil Kottantharayil, "Optimization of ICP-CVD Silicon Nitride for Si Solar Cell Passivation" in 38th IEEE Photovoltaic Specialist Conference 2012, Austin, USA, Dec. 2012.
  11. Abhishek Mishra, Mayur Waikar, Amit Gour, Hemen Kalita, Meenakshi Bhaisare, Mohammed Aslam and Anil Kottantharayil, "Large Memory Window Floating Gate Flash Memory with Multilayer Graphene as Charge Storage Layer" in proceedings of the International Memory Workshop 2012, Milano, Italy, Dec. 2012.
  12. Hasanali Virani, Suresh Gundapaneni and Anil Kottantharayil, "Optimization of Silicon ?-channel Tunnel FET with Dual ? Spacer" in 42nd Solid State Device Meeting (SSDM-2010), Tokyo, Japan in September, Dec. 2010.
  13. Hasanali Virani, David Esseni and Anil Kottantharayil, "Impact of electron velocity on the ION of n-TFETs" in Proceedings of the 40th European Solid State Device Research Conference, Dec. 2010.
  14. Hasanali G. Virani and Anil Kottantharayil, "Optimization of Hetero Junction n-channel Tunnel FET with High-k Spacers" in 2nd INTERNATIONAL WORKSHOP ON ELECTRON DEVICES AND SEMICONDUCTOR TECHNOLOGY , Dec. 2009.
  15. Hasanali G. Virani, Rama Bhadra Rao, Vishwanath Nikam and Anil Kottantharayil, "Investigation of Novel Si/SiGe Hetero Structures and Gate Induced Source Tunneling for Improvement of P-channel Tunnel FETs" in 41st Solid State Device Meeting (SSDM-2009), Sendai, Japan, Dec. 2009.
  16. Hasanali G. Virani, Rama Bhadra Rao and Anil Kottantharayil, "Anil Kottantharayil, Optimization of P-channel Tunnel FETs using High k spacers" in 15th International Workshop on the Physics of Semiconductor Devices, Dec. 2009.
  17. Hasanali G. Virani, Rama Bhadra Rao and Anil Kottantharayil,, " Optimization of P-channel Tunnel FETs using High k spacers," in 15th International Workshop on the Physics of Semiconductor Devices, Dec. 2009.
  18. Thakker, R.A., Patil, M.B., Anil, K.G, "Parameter extraction for advanced MOSFET model using particle swarm optimization" in Technical Proceedings of the 2008 NSTI Nanotechnology Conference and Trade Show, NSTI-Nanotech, Nanotechnology, Dec. 2008.
  19. Nikam, V., Bhuwalka, K.K., Kottantharayil, A, "Optimization of n-channel tunnel FET for the sub-22nm gate length regime," in Device Research Conference - Conference Digest, DRC, Dec. 2008.
  20. Thakker, R.A., Gandhi, N., Patil, M.B., Anil, K.G., "Parameter extraction for PSP MOSFET model using particle swarm optimization" in Proceedings of the 14th International Workshop on the Physics of Semiconductor Devices, IWPSD, Dec. 2007.
  21. Ramos, J., Augendre, E., Kottantharayil, A., Mercha, A., Simoen, E., Rosmeulen, M., Severi, S., Kerner, C., Chiarella, T., Nackaerts, A., Ferain, I., Hoffmann, T., Jurczak, M., Biesemans, S., "Experimental evidence of short-channel electron mobility degradation caused by interface charges located at the gate-edge of triple-gate FinFETs" in ICSICT-2006: 2006 8th International Conference on Solid-State and Integrated Circuit Technology, Proceedings, Dec. 2007.
  22. Chopde, A.M., Khandelwal, S., Thakker, R.A., Patil, M.B., Anil, K.G, " Parameter extraction for MOS model 11 using particle swarm optimization" in Proceedings of the 14th International Workshop on the Physics of Semiconductor Devices, Dec. 2007.
  23. Jurczak, M., Collaert, N., Rooyackers, R., Kottantharayil, A., Dixit, A., Ferain, I., San, T., Son, N.-J., Lenoble, D., Zimmerman, P., De Keersgieter, A., Von Arnim, K., Ramos, J., Mercha, A., Verheyen, P, "MUGFET - Alternative transistor architecture for 32 nm CMOS generation" in Extended Abstracts of the Sixth International Workshop on Junction Technology, IWJT, Dec. 2006.
  24. Dixit, A., Anil, K.G., Baravelli, E., Roussel, P., Mercha, A., Gustin, C., Bamal, M., Grossar, E., Rooyackers, R., Augendre, E., Jurczak, M., Biesemans, S., De Meyer, K., " Impact of stochastic mismatch on measured SRAM performance of FinFETs with resist/spacer-defined fins: Role of line-edge-roughness" in Technical Digest - International Electron Devices Meeting, IEDM, Dec. 2006.
  25. Van Dal, M.J.H., Collaert, N., Doornbos, G., Vellianitis, G., Curatola, G., Pawlak, B.J., Duffy, R., Jonville, C., Degroote, B., Altamirano, E., Kunnen, E., Demand, M., Beckx, S., Vandeweyer, T., Delvaux, C., Leys, F., Hikavyy, A., Rooyackers, R., Kaiser, M., Weemaes, R.G.R., Biesemans, S., Jurczak, M., Anil, K., Witters, L., Lander, R.J.P, " Highly manufacturable FinFETs with sub-10nm fin width and high aspect ratio fabricated with immersion lithography" in Digest of Technical Papers - Symposium on VLSI Technology, Dec. 2006.
  26. Lenoble, D., Anil, K.G., De Keersgieter, A., Eybens, P., Collaert, N., Rooyackers, R., Brus, S., Zimmerman, P., Goodwin, M., Vanhaeren, D., Vandervorst, W., Radovanov, S., Godet, L., Cardinaud, C., Biesemans, S., Skotnicki, T., Jurczak, M, " Enhanced performance of PMOS MUGFET via integration of conformal plasma-doped source/drain extensions" in Digest of Technical Papers - Symposium on VLSI Technology, Dec. 2006.
  27. Dixit, A., Anil, K.G., Mercha, A., Collaert, R., Brus, S., Richard, O., Rooyackers, R., Goodwin, M., Jurczak, M., De Meyer, K, "Towards optimally shaped fins in p-channel tri-gate FETs: Can fin height be reduced further?" in International Symposium on VLSI Technology - VLSI-TSA-TECH, Proceedings of Technical Papers,, pp.112-113, Dec. 2005.
  28. Snow, J., Vos, R., Anil, K.G., Kraus, H., Xu, K., Grinninger, F., Wagner, G., FKovacs, Mertens, P.W., "Selective etching of sige for removal of dummy layers in fully silicided gate architectures, " in ECS Transactions, Dec. 2005.
  29. Dixit, A., Anil, K.G., Collaert, N., Rooyackers, R., Leys, F., Ferain, I., De Keersgieter, A., Hoffmann, T.Y., Loo, R., Goodwin, M., Zimmerman, P., Caymax, M., De Meyer, K., Jurczak, M., Biesemans, S, "Parasitic source/drain resistance reduction in N-channel SOI MuGFETs with 15nm wide fins," in Proceedings - IEEE International SOI Conference, pp.226 - 228, Dec. 2005.
  30. Kubicek, S., Veloso, A., Anil, K.G., Hayashi, S., Yamamoto, K., Mitsuhashi, R., Kittl, A., Lauwers, M., Van Dal, S., Horii, Harada, Y., Kubota, M., Niwa, M., De Gendt, S., Heyns, M., Jurczak, M., Biesemans, S., "Ni-FUSI on high-k as a candidate for 65nm LSTP CMOS" in IEEE VLSI-TSA - International Symposium on VLSI Technology - VLSI-TSA-TECH, Proceedings of Technical Papers, pp.99-100, Dec. 2005.
  31. Henson, K., Collaert, N., Demand, M., Goodwin, M., Brus, S., Rooyackers, R., Van Ammel, A., Degroote, B., Ercken, M., Baerts, C., Anil, K.G., Dixit, A., Beckx, S., Schram, T., Deweerd, W., Boullart, W., Schaekers, M., De Gendt, S., De Meyer, K., Yim, Y., Hooker, J.C., Jurczak, M., Biesemans, S, "NMOS and PMOS triple gate devices with mid-gap metal gate on oxynitride and Hf based gate dielectrics IEEE VLSI-TSA" in International Symposium on VLSI Technology - VLSI-TSA-TECH, Proceedings of Technical Papers, pp.136-137, Dec. 2005.
  32. Dixit, A., Anil, K.G., Rooyackers, R., Leys, F., Kaiser, M., Weemaes, R., Ferain, I., De Keersgieter, A., Collaert, N., Surdeanu, R., Goodwin, M., Zimmerman, P., Loo, R., Caymax, M., Jurczak, M., Biesemans, S., De Meyer, K., "Minimization of the MuGFET contact resistance by integration of NiSi contacts on epitaxially raised source/drain regions" in Proceedings of ESSDERC 2005: 35th European Solid-State Device Research Conference, pp.445-448, Dec. 2005.
  33. Kittl, J.A., Lauwers, A., Pawlak, M.A., Demeurisse, C., Anil, K.G., Veloso, A., Van Dal, M.J.H., Schram, T., Brijs, B., Kaiser, M., Kubicek, S., Cunniffe, J., Verbeeck, R., Vrancken, C., Biesemans, S., Maex, K., "Materials issues of NI fully silicided (fusi) gates for CMOS applications" in Proceedings - Electrochemical Society, Dec. 2005.
  34. Pawlak, M.A., Kittl, J.A., Janssens, T., Lauwers, A., Vandervorst, W., Anil, K.G., Schram, T., Veloso, A., Van Dal, M.J.H., Maex, K., Vantomme,A, "Influence of activation annealing and silicidation process on as redistribution and pile-up at the NixSiy/SiO2 interface" in Proceedings - Electrochemical Society, Dec. 2005.
  35. Subramanian, V., Mercha, A., Dixit, A., Anil, K.G., Jurczak, M., De Meyer, K., Decoutere, S., Maes, H., Groeseneken, G., Sansen, W, "Geometry dependence of 1/f noise in n- and p-channel MuGFETs" in AIP Conference Proceedings, pp.279-282, Dec. 2005.
  36. Hoffmann, T., Doornbos, G., Ferain, I., Collaert, N., Zimmerman, P., Goodwin, M., Rooyackers, R., Kottantharayil, A., Yim, Y., Dixit, A., De Meyer, K., Jurczak, M., Biesemans, S., "GIDL (Gate-Induced Drain Leakage) and parasitic schottky barrier leakage elimination in aggressively scaled HfO2/TiN FinFET devices" in Technical Digest - International Electron Devices Meeting, IEDM,, Dec. 2005.
  37. Anil, K.G., Verheyen, P., Collaert, N., Dixit, A., Kaczer, B., Snow, J., Vos, R., Locorotondo, S., Degroote, B., Shi, X., Rooyackers, R., Mannaert, G., Brus, S., Yim, Y.S., Lauwers, A., Goodwin, M., Kittl, J.A., Van Dal, M., Richard, O., Veloso, A., Kubicek, S., Beckx, S., Boullart, W., De Meyer, K., Absil, P., Jurczak, M., Biesemans, S, "CMP-less integration of Fully Ni-Silicided Metal Gates in FinFETs by simultaneous silicidation of the source, drain, and the gate using a novel dual hard mask approach" in Digest of Technical Papers - Symposium on VLSI Technology,, Dec. 2005.
  38. Kittl, J.A., Veloso, A., Lauwers, A., Anil, K.G., Demeurisse, C., Kubicek, S., Niwa, M., Van Dal, M.J.H., Richard, O., Pawlak, M.A., Jurczak, M., Vrancken, C., Chiarella, T., Brus, S., Maex, K., Biesemans, S, " Scalability of Ni FUSI gate processes: Phase and Vt control to 30 nm gate lengths" in Digest of Technical Papers - Symposium on VLSI Technology,, Dec. 2005.
  39. Lauwers, A., Veloso, A., Hoffmann, T., Van Dal, M.J.H., Vrancken, C., Brus, S., Locorotondo, S., De Marneffe, J.-F., Sijmus, B., Kubicek, S., Chiarella, T., Pawlak, M.A., Opsomer, K., Niwa, M., Mitsuhashi, R., Anil, K.G., Yu, H.Y., Demeurisse, C., Verbeeck, R., De Potter, M., Absil, P., Maex, K., Jurczak, M., Biesemans, S., Kittl, J.A., " CMOS integration of dual work function phase controlled Ni FUSI with simultaneous silicidation of NMOS (NiSi) and PMOS (Ni-rich silicide) gates on HfSiON" in Technical Digest - International Electron Devices Meeting, IEDM, Dec. 2005.
  40. Anil, K.G., Veloso, A., Kubicek, S., Schram, T., Augendre, E., De Marneffe, J.-F., Devriendt, K., Lauwers, A., Brus, S., Henson, K., Biesemans, S., "Demonstration of fully Ni-silicided metal gates on HfO2 based high-k gate dielectrics as a candidate for low power applications" in Digest of Technical Papers - Symposium on VLSI Technology, pp.190-191, Dec. 2004.
  41. Kittl, J.A., Lauwers, A., Chamirian, O., Pawlak, M.A., Van Dal, M., Akheyar, A., De Potter, M., Kottantharayil, A., Pourtois, G., Lindsay, R., Maex, K, " Applications of Ni-based silicides to 45 nm CMOS and beyond" in Materials Research Society Symposium - Proceedings, pp.31-42, Dec. 2004.
  42. Veloso, A., Anil, K.G., Witters, L., Brus, S., Kubicek, S., De Marneffe, J.-F., Sijmus, B., Devriendt, K., Lauwers, A., Kauerauf, T., Jurczak, M., Biesemans, S, "Work function engineering by FUSI and its impact on the performance and reliability of oxynitride and Hf-silicate based MOSFETs" in Technical Digest - International Electron Devices Meeting, pp.855-858, Dec. 2004.
  43. Severi, S., Anil, K.G., Pawlak, J.B., Duffy, R., Henson, K., Lindsay, R., Lauwers, A., Veloso, A., De Marneffe, J.F., Ramos, J., Camillo-Castillo, R.A., Eyben, P., Dachs, C., Vandervost, W., Jurczak, M., Biesemans, S., De Meyer, K, "Diffusion-less junctions and super halo profiles for PMOS transistors formed by SPER and FUSI gate in 45 nm physical gate length devices" in Technical Digest - International Electron Devices Meeting, IEDM, pp.99-102, Dec. 2004.
  44. Anil, K.G., Henson, K., Biesemans, S., Collaert, N, "Layout density analysis of FinFETs " in Proceedings of the European Solid-State Device Research Conference, pp.139-142, Sep. 2003.
  45. Shrivastav, G., Mahapatra, S., Ramgopal Rao, V., Vasi, J., Anil, K.G., Fink, C., Hansch, W., Eisele, , " Performance optimization of 60 nm channel length vertical MOSFETs using channel engineering" in Proceedings of the IEEE International Conference on VLSI Design,, pp.475-478, Dec. 2001.
  46. V. Ramgopal Rao, S. Mahapatra,, J.Vasi, K. G. Anil, C. Fink, W. Hansch, and I. Eisele, "Hot-carrier performance of 60 nm channel length delta-doped vertical MOSFETs with high-pressure grown oxide as a gate dielectric" in 31st IEEE Semiconductor Interface Specialists Conference (SISC 2000), San Diego, California, Dec. 2000.
  47. Anil, K.G., Mahapatra, S., Eisele, I., "Role of inversion layer quantization on sub-bandgap impact ionization in deep-sub-micron n-channel MOSFETs" in echnical Digest - International Electron Devices Meeting,, pp.675-678, Dec. 2000.
  48. K. G. Anil, T. Pompl, I. Eisele, "Impact of Gate Oxide Thickness Scaling on Hot- Carrier Degradation in Deep-sub-micron nMOSFETs" in in Proceedings of the 30th European Solid-State Device Research Conference (ESSDERC), Cork, Ireland, pp.124-127, Sep. 2000.
  49. K. G. Anil, S. Mahapatra, I. Eisele, V. R. Rao and J. Vasi, "Drain bias dependence of gate oxide reliability in conventional and asymmetrical channel MOSFETs" in 30th European Solid-State Device Research Conference (ESSDERC 2000), Cork, Ireland, pp.132-135, Sep. 2000.
  50. K. G. Anil, S. Mahapatra, V. Ramgopal Rao and I. Eisele, "Comparison of Sub- Bandgap Impact Ionization in Deep-Sub-Micron Conventional and Lateral Asymmetrical Channel nMOSFETs" in in Proceedings of the International Conference on Solid State Devices and Materials (SSDM) , Sendai, Japan, pp.60-61, Aug. 2000.
  51. W. Hansch, K. Anil, P. Bieringer, C. Fink, F. Kaesen, I. Eisele, M. Tanaka and M. Miura-Mattausch, "Channel Engineering for the Reduction of Random-Dopant Placement-Induced Threshold Voltage Fluctuations in Vertical sub-100nm MOSFETs" in Proceedings of the 29th European Solid-State Device Research Conference (ESSDERC), Leuven, Belgium, pp.408-411, Sep. 1999.
  52. K. G. Anil, J. M. Vasi and R. K. Lal, "Low Dose Radiation Sensor for Medical Therapy Applications" in Proceedings of the Ninth International Workshop on Physics of Semiconductor Devices, New Delhi, India., pp.1145-1148, Dec. 1997.

Patents

  1. Sandeep S. S., Anil Kottantharayil"A Method for Etching Silicon Substrates", Patent filed in May 2012 (India).
  2. Robin Singla, Trupti, and Anil Kottantharyail"Functionalization of Graphene", Patent filed in October 2015 (India).
  3. Kottantharayil, Anil, Loo, Roger"Multiple gate semiconductor device and method for forming same ", Patent filed in January(US).
  4. Kottantharayil, Anil"Method for doping fin-based semiconductor device", Patent filed in April(japan).
  5. Kottantharayil, Anil"Method for doping a fin-based semiconductor device", Patent filed in April(US).
  6. Kottantharayil, Anil"Method for doping a fin-based semiconductor device", Patent filed in April(Europe).
  7. Jim John, Mehul Rawal, Chetan Singh Solanki, Anil Kottantharayil"A system for extracting water from air for drinking and cleaning purposes and a method thereof", Patent filed in October 2011 (India).
  8. Kottantharayil, Anil"Multiple gate semiconductor device and method for forming same", Patent filed in January(Europe).
  9. Kottantharayil Anil, Loo Roger"Multilayer gate semiconductor device and manufacturing method therefore", Patent filed in January(Japan).
  10. Kittl, Jorge Adrian, Lauwers, Anne, Veloso, Anabela, Kottantharayil, Anil, van Dal, Marcus Johannes Henricus"Method for Forming Dual Fully Silicided Gates and Devices with Dual Fully Silicided Gates", Patent filed in February(United States of America).
  11. Kittl Jorge Adrian, Lauwers Anne, Veloso Anabela, Kottantharayil Anil, Van Dal Marcus Johannes Henric"Method of forming dual fully silicided gate and device obtained by the method", Patent filed in February(japan).
  12. Kittl Jorge Adrian, Lauwers Anne, Veloso Anabela, Kottantharayil Anil, Van Dal Marcus Johannes Henric"Formation method for fully silicided gate MOSFET and device obtained by the same method", Patent filed in March(japan).

Editor

  1. S. Kalaivani and Anil Kottantharayil, "Spray coated aluminum oxide thin film for P-type crystalline silicon surface passivation", IEEE, Jun. 2015.

Contributed Chapters To A Book

  1. J. Kittl, A. Lauwers, O. Chamirian, M. Kmieciak, M. van Dal, A. Veloso, A. Kottantharayil, G. Pourtois, M. de Potter de ten Broeck, K. Maex, "Materials for Information Technology: Devices, Interconnects and Packaging ", Silicides - Recent advances and prospects, Springer Verlag.

Other Professional Activities

  1. Organizing committee co-chair, 2nd INTERNATIONAL WORKSHOP ON ELECTRON DEVICES AND SEMICONDUCTOR TECHNOLOGY (IEDST 2009) June 1-2, 2009, Indian Institute of Technology Bombay, Mumbai, India.
  2. Senior Member of IEEE since 2008 and member since 1997
  3. Member of the Materials Research Society
  4. Publicity Chair and member of program committee, International Workshop on Physics of Semiconductor Devices (IWPSD) 2007, Mumbai, India
  5. Poster committee chair of International Conference on Nano science and Technology (ICONSAT-2010), February 17 - 20, 2010, Indian Institute of Technology Bombay, Mumbai, India.
  6. Reviewer for the following journals: IEEE Transactions on Electron Devices IEEE Electron Device Letters IEEE Transactions on Nanotechnology Applied Physics Letters Progress in Photovoltaics: Research and Applications Journal of Applied Physics Materials Science and Engineering (B)