Department of Electrical Engineering, Indian Institute of Technology Bombay
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2.5D / 3 D Integration Technology for CMOS
Dr. Mukta Ghate Farooq, FIEEE GlobalFoundries Fellow, GlobalFoundries, USA
Venue, Date and Time

Victor Menezes Convention Centre (VMCC) Room No. 21, Mar 10, 2017, 09:45 AM
Abstract

2.5D/3D integration technology encompasses a wide variety of configurations which employ TSVs (Through Silicon/Substrate Vias) in a silicon wafer. 2.5D generally refers to heterogeneous integration of chips using interposers which typically have only passive components: wiring, capacitors and inductors. 3D technology goes beyond the interposer by integrating logic functionality in the assembly. 3D integration has the ability to enhance system performance by increasing bandwidth, reducing wire delay, and enabling better power management. In 3D technology, the TSVs may be integrated into the CMOS transistor fabrication at a number of points in the manufacturing sequence. Key considerations to determine the optimal introduction point include the size of the TSV, dimensional compatibility of the TSV with the BEOL (Back End Of Line) features, and the wiring design requirements. In this talk, we will review the various types of 2.5D and 3D integration, and why they offer significant advantages over conventional methods. We will also discuss the key elements of TSV fabrication including via etching, insulation, metallization, annealing, capping, as well as wafer grindside processing. Finally we will discuss the effects of TSVs on devices and BEOL structures, and the type of reliability testing that is required to evaluate the long-term impact of TSVs.
About the Speaker

Dr. Mukta Ghate Farooq, a GlobalFoundries Fellow, is the technology leader for 7 nm Advanced Silicon Packaging. She is a metallurgist and materials scientist, with expertise in 2.5D/3D integration, Through Silicon Via (TSV), die stacking, C4, BGA, CGA, lead-free alloys, chip package interaction, Back End and Far Back End of Line structures, and intellectual property development. She has led numerous technology programs to successful qualifications, including 3D 32 nm CMOS technology with Cu TSV, 2.5D heterogeneous interposer technology, and lead-free interconnects for CMOS die at multiple nodes. Mukta holds 190 granted patents and was designated Lifetime Master Inventor and Academy of Technology Member at IBM, as well as GlobalFoundries Master Inventor. She has several external publications, including invited papers, and has taught short courses and tutorials. Mukta is an IEEE Fellow, IEEE EDS Distinguished Lecturer, and EDS Governor. She received her BTech from IIT Bombay, MS from Northwestern University, and PhD from Rensselaer Polytechnic Institute.