Department of Electrical Engineering, Indian Institute of Technology Bombay
IITB Calendar

3D Monolithic Integration for advanced CMOS and towards neuromorphic systems
Dr. Veeresh Deshpande, IBM-Zurich Research Laboratory
Venue, Date and Time

Nano Conference room, Jul 06, 2017, 11:30

Advanced CMOS technology with 2D planar integration of devices is facing serious challenges in terms of area scaling due to lithographic limitations. 3D monolithic (3DM) integration has the potential to achieve very high circuit densities without device scaling, due to high granularity provided by transistor level stacking. Besides conventional digital circuits, it offers the opportunity to stack novel materials, different functional layers (such as memories) at transistor level for providing pathway towards non-Von-Neumann computing. Although significant development has been done on Si(Ge)-over-Si 3D monolithic integration, limiting degradation of bottom layer FET due top layer FET thermal budget still remains as a major challenge. III-V materials, owing to their low process temperature, are well suited to be top layer FETs. Also, high-mobility III-V materials are being considered for replacing strained Si in nFETs for sub-7 nm nodes. In this talk, I will discuss our efforts towards developing a 3D monolithic integration platform of InGaAs-over-Si(Ge). I will detail the III-V device integration and 3D CMOS circuits utilized as test-vehicles to demonstrate the 3D monolithic platform. Based on this learning, I will discuss the current efforts towards integration of resistive memory (RRAM) devices in the 3D monolithic stack, particularly targeting neuromorphic applications. I will discuss the benefits, possible material options and future integration plans.
About the Speaker

Dr. Veeresh Deshpande graduated with a Masters in Physics from Indian Institute of Technology Madras, India in 2009 and obtained a PhD in Applied Physics from CEA-LETI/University of Grenoble, France in 2012. He carried out PhD thesis research on Si nanowire MOSFETs for CMOS and beyond-CMOS quantum computing applications. After his PhD, he worked as a Staff Research Engineer at IBM SRDC (India) from 2012-14, involving in development of patterning solutions for advanced CMOS nodes. Since 2014, he is with IBM-Zurich Research Laboratory (Switzerland), where his research work is focused on III-V device integration for CMOS, 3D integration and devices for neuromorphic systems. He is leading the integration efforts for 3D Monolithic Integration of III-V materials and resistive memory with Si CMOS targeting More-than-Moore and neuromorphic computing applications.