Silicon (Si) and its oxide (SiO2) have been the workhorse of scaling driven semiconductor industry. Almost a decade ago, IBM announced high-k metal gate in 32-nm technology node, wherein Hafnium oxide (HfO2) together with Titanium nitride (TiN) were used in the gate stack as preferred high-k dielectric, and metal respectively. The performance of these scaled Complementary Metal-Oxide-Semiconductor (CMOS) devices (32-nm and beyond) rely on accurate control of materials in the bulk and at the interfaces in terms of chemical composition, nature of atomic species, and defects. The defects in gate oxides and at their interfaces influence the threshold voltage shift, and the mobility degradation. The chemical composition, and the nature of atomic species at the source/drain contact, and metal interconnects strongly impact the resistances. In this talk, we will discuss some of these fundamental problems in scaled CMOS devices, and solutions through first principles-based modelling approach. Further, we will discuss about achieving the device performance targets through materials innovation, and engineering, using the first principles modelling based on the density functional theory.
Rajan Pandey has Ph.D. degree in Physics from Indian Institute of Technology Kanpur. He then carried out post-doctoral research in the department of Chemistry, University of California at Irvine. Rajan Pandey has spent more than a decade in the semiconductor research and development at IBM Microelectronics, and GLOBALFOUNDRIES, where he was engaged in multi-scale materials modelling to support the development of five generations of Complementary Metal-Oxide-Semiconductor technologies. Rajan Pandey has co-authored more than 40 research papers in peer reviewed international journals and conferences, and over 10 patents in the United States.