As the scaling of logic and memory devices slows down due to technological and cost challenges. Semiconductor Industry has explored packaging innovations to improve the system level performance, bandwidth, form factor and power dissipation. In this talk we will discuss the key technologies enabling this improvement. 3D TSV: Through Silicon Via (TSV) has a potential to stack multiple homogenous or heterogeneous dies. In particular, it has demonstrated a stacking of DRAM dies to achieve high bandwidth. We will go through the process challenges which affect the electrical parametric and reliability specifications of TSV. Flipchip Microbump: As the logic die I/O pad density increases, there is a demand to scale the Microbump polyimide opening which in turn leads to under bump metallization contact resistance (UBM Rc) issue. We will have a deep dive into the issue and understand the need of advanced PVD pre clean to minimize the UBM Rc. RDL: Redistribution layer (RDL) is a wafer level packaging interconnects technology. It enables FANOUT packaging to reduce overall package thickness, gain speed, and better power consumption as required in smartphones. We will briefly touch up on fine pitch RDL sheet resistance issue, and discuss integration scheme in detail. Prerequisite: EE669 VLSI Technology or basic understanding of semiconductor unit processes.
Bharat Bhushan is an alumnus of IITB, graduated with B.Tech/ M.Tech in EE in 2011. He is a semiconductor R&D professional. Previously from Dec 2014 to Jan 2018, he was a Principal engineer with Global Foundries for TD&R of STT-MRAM; recipient of spotlight and patent recognition awards in 2016 and 2017. From Aug 2011 to Dec 2014, he was with Applied Materials as a senior engineer for Advanced Packaging R&D; awarded with employee of the quarter award in 2013. In summer 2009, he was a research intern with IBM SRDC for TCAD simulation of GIDL in 45nm CMOS. His dual degree thesis was on compact modeling of TFET; recipient of institute academic award in 2009. He holds 12 US patents issued/ pending, and authored 6 research papers in international journals/ conferences.