Bias temperature instability is a key aging phenomenon that causes CMOS circuit performance to degrade over time. Traditionally, this has been addressed either by ignoring it altogether or by placing a generic margin on a circuit. As the magnitude of this effect becomes more important, solutions from the architecture level to the circuit level are required to account for this effect during the process of integrated system design. A key ingredient is to connect detailed models that have been presented at the device level to those that operate at higher levels of abstraction, such as the logic level or the architecture level. This talk will present an overview of such methods and discuss recent research directions on this topic. Specifically, solutions that optimize circuit performance under aging degradations at both the presilicon stage, while the circuit is being designed, and the postsilicon stage, when the circuit is in operation in the field, will be discussed.
Sachin Sapatnekar received his BTech from IIT Bombay in 1987, his MS from Syracuse University in 1989, and his PhD from the Univ. of Illinois at Urbana-Champaign in 1992. He is currently at the Univ. of Minnesota, where he holds the Distinguished McKnight University Professorship and the Henle Professorship in the ECE dept. He has been the Editor-in-Chief of the IEEE Transactions on CAD, the General Chair for the ACM/IEEE Design Automation Conference (DAC), and the Technical Program Co-Chair for the International Symposium on VLSI Design. He is a recipient of the NSF Career Award, six conference Best Paper Awards(3 at DAC, 1 each at ICCD, ISPD, and ISQED) and a Best Poster Award (IRPS). He has received the Semiconductor Research Corporation's Technical Excellence Award (2003), the Semiconductor Industry Association University Research Award (2013), and he is a Fellow of the IEEE. He was a Senior Fulbright Scholar at the Polytechnic University of Catalonia (UPC) in Spain in 2013, and is currently a D.J. Gandhi Visiting Professor at IIT Bombay.