With aggressive scaling of transistor dimensions, contact resistance (Rc) between the source/drain and metal is becoming increasingly important due to its ever increasing fractional contribution to the total transistor resistance. Transistors with higher contact resistance exhibit higher intrinsic gate delay, higher energy dissipation per switching, and less current saturation – affecting system level performance. In the first part of the talk, I shall explain why reliable extraction of ultra-low specific contact resistivity (?c) is very challenging using conventional test structures like transfer length method (TLM), and then discuss the design of a novel test structure, called sidewall TLM (STLM), by etch modification of TLM process flow. Both the median and standard deviation of the extracted ?c values obtained from a 300mm wafer scale process flow will be shown to improve significantly in STLM compared with the results from TLM. With silicide as a control, detailed design optimization and manufacturability issues of MIS contacts will be discussed and the results obtained from optimized MIS STLM process flow will be presented and benchmarked against silicide data at similar doping conditions. Quantum transport simulation and XPS measurement results will also be discussed in such contact structures to understand the Schottky barrier height (SBH) tuning mechanism. In the second part of the talk, doping and contact challenges of 2D Transition metal dichalcogenide (TMD) channel MOSFET will be discussed. This will be followed by discussion of a chemical doping technique which enhances the doping density in such 2D films and hence reduces the contact resistance by an order of magnitude. Such a reduced contact resistance will be shown to improve the saturated drive current of a 100nm Lg MoS2 channel FET to a record high number of 0.46 mA/?m.
Dr. Majumdar obtained his B.E. from Jadavpur University in 2003, M. Tech. from Indian Institute of Technology Delhi in 2005 and PhD from Indian Institute of Science Bangalore in 2011. From July 2005 to December 2006, he was with Magma Design Automation working on interconnect modeling and timing analysis. Since 2011, he is working as an emerging technology research scientist in the Process Technologies group at SEMATECH, Albany, New York, where he focuses on the theory, experiments and process module developments for advanced electronic devices using conventional and emerging materials including Si, III-V, Ferroelectrics, graphene and TMD.