With an unprecedented growth in computing technology, the twentieth century has paved the way for an information revolution. More than the high volumes of data that are stored in and retrieved from the cloud, the analysis that is happening around this data is the major contributor for the computational challenges associated with Big Data. Hence, achieving fast and energy-efficient Big Data analytics is vital to enable modern discoveries across numerous fields, including medicinal research, genetic analysis, financial market analysis and astrophysical research. Traditional Big Data analytics employ server farms, where racks of servers are interconnected through multiple layers of electrical switches. This traditional approach has serious limitations in terms of computation scalability, network reliability and power consumption. In an era when power constraints and data movement are proving to be significant barriers for high-end computing, manycore architectures offer a low power and highly scalable platform suitable for both data and compute-intensive applications. Despite the promise and the recent advances in silicon integration technology, designing manycore platforms remains a highly challenging task. Tackling memory and power walls, establishing low-latency global interconnects and handling thermal hotspots are few of the challenges involved in crafting high performing manycore platforms. Towards addressing these challenges, this seminar is focused on designing latency and energy efficient Network-on-Chip (NoC) architectures for emerging applications. The contents of the seminar include 1. An extensive discussion on the on-chip traffic patterns induced by today’s manycore applications 2. Limitations of today’s industry standard NoCs 3. Designing scalable network topologies and developing suitable data transfer algorithms for NoCs 4. Optimizing the power consumption of the NoCs
Karthi Duraisamy is currently a senior Research and Development (R&D) Engineer at Synopsys Inc., California. In Synopsys, his R&D work is focused on the synthesis of digital circuits. Karthi graduated from Washington State University in December 2017, with a PhD degree in Computer Engineering. His PhD dissertation, titled “Collective Communication-Aware High-Performance Network-On-Chip Architectures for Big Data Processing”, discusses the challenges associated with designing ultra-low latency on-chip networks and proposes efficient solutions. In May 2013, Karthi received his M. Tech in Electronics and Electrical Communication Engineering from IIT Kharagpur. He received his bachelors in Electronics and Communication Engineering from College of Engineering Guindy in 2010. His research interests include, design of scalable high-performance manycore platforms and hardware accelerators to address the computational challenges of emerging applications, leveraging passive optical components to design high bandwidth low power data center interconnects and developing machine learning assisted methodologies for the synthesis of digital circuits.