Continuous-time Delta Sigma Modulators based on 1-bit quantizers with FIR feedback combine the advantages of single-bit and multibit operation. At GHz clock rates, even the FIR-DAC approach begins to run into difficulties due to the limited time available for regeneration. This work uses a time-interleaved 1-bit ADC and 8-tap FIR-DACs to address this problem. Digital calibration (implemented off-chip) addresses mismatch in the interleaved sections, and rise-fall asymmetry in the feedback DAC waveforms. Experimental results from fabricated chips demonstrate an ADC that achieves true 11 bit performance in 60MHz bandwidth when clocked at 6 GHz in a UMC-65nm low leakage process, while consuming about 13mW. Further, Bench characterization of wide band oversampled converters is a challenge due to the high data rate at the output of the modulator. We propose the use of a duo binary test interface to extend the frequency range over which reliable laboratory measurements become possible. We show that using such an interface effectively randomizes the modulator output data and reduces high frequency content, thereby reducing the bandwidth demands made on the test equipment. It also reduces degradation of the modulator performance caused by package feed-through effects. Experimental results from a test chip in 90nm CMOS show that the proposed interface extends the upper sampling frequency limit of an existing single-bit CTDSM from 3.6 GHz to 4.4 GHz.
Ankesh Jain received the Ph.D. degree from the Indian Institute of Technology, Madras, in 2016, where worked on the design and characterization of high speed continuous-time delta-sigma converters. He is currently a Post-Doctoral Researcher with the University of Ulm, Germany. His research interests are in the areas of data-conversion and phase-lock techniques. He was a recipient of the ISCAS 2013 Best Student Paper Award.