There is an effort given to the design and development of switched capacitor based DC-DC converter suitable for high drop-out and embedded applications. The target is for embedded applications (without external capacitor) and hence, key objectives are to reduce capacitors size, to enhance the power efficiency of the converter, and maintaining the output voltage ripple within acceptable range. In the proposed approach, along with a linear regulator switched capacitors are used to recycle charge for improving power efficiency. The calculation of the power efficiency is carried out. Apart from line and load regulation the linear regulator helps to reduce the output ripple which is originated in the switching circuit. Ripple reduction which is provided by the linear regulator is analyzed and optimized. The higher frequency output ripple which lies beyond the regulation loop bandwidth is reduced by introducing a synthesized ripple in opposite phase through the linear regulator. Feeding of this synthesized ripple is such that its effect at the converter output counters the original ripple and hence, the resultant output ripple becomes very small. The circuit details of each of the individual functional blocks along with their simulation results are given in a very vivid manner. The measurement results and the post measurement analysis of the fabricated test chip of the above converter validate well the proposed ripple reduction techniques. However, the ripple at the converter output is still alarmingly high. Moreover, in case of embedded DC-DC converters during switching transition a short circuit path from main supply (Vdd) to ground is created due to finite overlap duration of control signals. This eventually degrades the power efficiency of the converter in the form of shoot-through current loss. To eliminate the shoot-through current loss, a non-overlapped rotational time interleaving (NRTI) switching scheme is proposed and hence, the power efficiency is increased. It also helps to keep the ripple within acceptable range. The design implementation of the NRTI switched capacitor based converter is done along with different regulation schemes. Last but not the least, the same set of flying capacitors are used to provide three different step-down fractions (viz., Vdd/2, Vdd/3 and 2Vdd/3) of its input supply to meet the different technology nodes and hence the area efficiency of the converter is increased. It has also load sensing circuit which helps to dynamically reconfigure the switch capacitor circuit module based on the instantaneous load requirement. This feature enables to extend the load current range to a higher limit and at the same time improves power efficiency in low load current regime. The power efficiency is improved and it also remains high over a wide range of load current with the use of hybrid control regulation.
Kaushik Bhattacharyya received his B.Tech. Degree in Electronics and Telecommunication Engineering from the University of Kalyani, WB, India in the year of 2000 and M.S. and Ph.D. Degree from the Department of E&ECE;, IIT-Kharagpur, India in 2004 and 2011, respectively. He achieved INAE Best PhD Project Award in 2011. He had worked for IME, Singapore and APM-Bangalore, India. Presently, he is engaged in teaching with an Engineering college located in Bangalore, India. To his credit he has nine publications in the reputed international journals and seven publications in the international and national conferences, yet. Kaushik is also a senior member of IEEE. His Research interest includes Analog and Mixed Signal Circuit Design and VLSI Architectural Design.