FinFETs are emerging as the devices of choice for the 20nm node and beyond. They alleviate the leakage and the short channel bottlenecks reached by planar technologies, but they also introduce new design challenges for IP development, which require knowledge of and experience in designing with FinFETs to ensure design success. This talk addresses the benefits and challenges of transitioning from planar to FinFET technologies, goes over lithography options for manufacturing FinFETs and FinFETs implications for IP design.
Jamil is currently a Synopsys Scientist in the Solutions Group at Synopsys working on advanced nodes technology development for memories and IP. He is also a member of Synopsys’ Technology Roadmap Team and Synopsys’ Patent Committee. He was recently Group Director of R&D of the Implementation Group of Synopsys (IG) overseeing projects in 3-D IC and SIP design. He has been with Synopsys since 1998 where he originally managed the Memory Compiler and IO design groups before joining the Advanced Technology Group (ATG) where he worked on DFM / DFY, 3-T SRAM technology, corrugated substrate technology (for FinFET manufacturing), low power design, and Structured ASICs research including designing and implementing 3 test chips covering on-chip DFM issues, low power, and a Structured ASIC architecture. Jamil also co-authored the book “Design for Manufacturability and Yield for Nano-scale CMOS published by Springer in 2007. Before joining Synopsys Jamil managed circuit design at Chips and technologies and worked in the circuit design area at several companies. Jamil was the chairman of the Custom Circuits committee of CICC for 2005-2007and has served on the technical program committee of CICC from 2001 to 2007. He holds 11 issued patents and 9 pending ones in the areas of circuits and design architecture and is the author / co-author of over 20 papers and articles.