The logical abstractions which delineate hardware and software are becoming ever thinner, thereby prompting principled hardware-software co-design practices. I identify three forces that are accelerating this trend: arriving at the limits of traditional CMOS technology scaling, need for hard guarantees in cyber-physical systems, and the emergence of a dominant computational workload in the form of machine learning. In this talk, I will first give an overview of my research work on hardware-software co-design spanning academia and industry. I will then exemplify such work for a specific problem of scheduling on thermally-throttled processors. The question of interest is: "How can we guarantee worst-case execution times on processors which experience Dynamic Voltage/Frequency Scaling triggered by high on-chip temperatures"? In particular, I will describe how the formalism of min-plus algebra can be used to specify and analyse timing traces. Then, abstracting out, I shall provide my perspective on machine learning and its impact on hardware design. I will identify few open research problems on hardware-software co-design for machine learning. Finally, I will end with two proposals for courses that can be taught in this area.
Pratyush Kumar is an alumnus of IIT Bombay. In 2009, he finished his Dual Degree from EE, specialising in VLSI design. He holds a PhD from the EE department at ETH Zurich. His doctoral research focused on hardware-software co-design for cyber-physical systems, especially timing analysis. He has worked for over 2.5 years at IBM Research in the areas of smart energy and machine learning. Currently, he is a consulting researcher at Multicoreware. Pratyush has published over 30 research papers in IEEE and ACM publications, and holds 5 patents at the US PTO.