The capacity of hardware (integrated circuit or FPGA) has been increasing every year, while the ability to design hardware has been more or less stagnant. Based on this premise, we have been working on tools which can make the hardware design process easier. The primary contribution is a set of tools which start with an algorithm described as a collection of interacting threads and produce a logic circuit which is equivalent to the algorithm description in a certain sense. However for such a tool-set to be practically useful, it should satisfy the following requirements: - it should accept generic code written in a high level language as a starting point. - it should produce circuits that are provably equivalent to the high-level code. - it should produce circuits that are efficient relative to those produced using "human" efforts. The AHIR tool-set meets these requirements to a certain extent. In this talk, I will describe the basic transformations used in the AHIR tool-set in order to go from algorithm to hardware. I will also describe two of the important optimizations that the tool set performs: memory decomposition and loop pipelining. Finally I will present some experimental data about the use of this tool-set in various use-scenarios. The tool-set is a work in progress and is available to all under an open source license.
Madhav Desai received his Btech degree in Electrical Engineering from IIT Bombay in 1984, and his MS and PhD degrees in Electrical Engineering from University of Illinois, Urbana-Champaign in 1991. He was the Principal Engineer at Digital Equipment Corporation during 1992-96. Since 1996 he has been at IIT Bombay, where he is currently a Professor in the Electrical Engineering department. His interests include circuits and systems.