There has been an increase in the demand for flash memories due to tremendous increase in sale of hand-held devices like tablets, smart phones, digital cameras etc. However, further scaling of NAND flash memories have shown profound limitations due to significantly degraded performance and reliability. NAND Flash manufactures have begun the quest for a new technological solution. The most promising emerging technology solution which can replace NAND flash is Resistive Switching Memories (RRAM). Besides this, RRAM can also fill in the latency gap between DRAM and NAND flash memories, serving as new class of non-volatile memories. HfOx is a mainstream oxide in the fab and is a strong candidate for RRAM. In the first part of the talk, I will cover the trade-off between various HfOx RRAM performance parameters (low resistance state (LRS), high resistance state (HRS), operating voltages and currents as well as pulse speed) which are required to demonstrate its feasibility as NAND flash replacement. I will also cover the impact of switching speed on the cycle to cycle variability in these devices. In the second part of the talk, I shall be covering the next generation logic devices. To sustain continuous scaling of CMOS logic technology requires new technology solutions. One approach to continuing performance gains as CMOS scaling matures is to replace the strained silicon MOSFET channel with an alternate material offering a higher mobility than strained silicon. Candidate materials include Ge, SiGe, and a variety of III-V compound semiconductors. However introduction of non-silicon channel materials pose serious reliability challenges. In this section of presentation I shall be covering PBTI and NBTI reliability challenges in SiGe and III-V channel respectively. The effects of PBTI stress in InGaAs channel n-MOSFET with gate first and gate last process flow are investigated by performing stress and recovery measurements and identifying different degradation components. Also the impact of Ge% on the NBTI in SiGe channel devices is covered.
Dr. Shweta Deora obtained her B.E. from Sardar Patel University, Gujarat in 2004 and PhD from Indian Institute of Technology Bombay in 2011. From 2005 to 2006 she was working as research assistant on the radiation sensor development project with IIT-Bombay. Since July 2011, she has been with SEMATECH, Albany, NY, working as device engineer in Process technology (PT) group where she focusses on resistive random-access memory and high mobility channel MOSFET devices. She works on test structure development, process optimization, electrical characterization and reliability for advanced logic and memory devices including III-V, SiGe, Ge, TMD, RRAM with various oxides and MTJ.