Mind boggling scaling of CMOS technologies for last five decades is an unparalleled engineering feat. This has been the source of the spectacular rise of the microelectronic industry. The Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) has been scaled to reduce the cost of fabrication by packing more transistors onto the same area. The reduced dimensions also result in a reduction of the time taken by an electron to move from source to drain and thus improving the performance of the device. In addition to the scaling of physical dimensions, a number of modifications were made to the device structure that have played a vital role in order to keep Moore's law alive. The two major changes were: (a) adopting high-$\kappa$ gate oxide when scaling of the then existing SiO$_2$ was no longer feasible; (b) adopting multigate architectures to maintain the electrostatic integrity and improve the drive current of the devices at extremely small channel lengths. These technology innovations have made the oxide-semiconductor interface more important than ever before. In fact, it has already been shown with simulations that the scattering due imperfections at the oxide-semiconductor is today the dominant cause of mobility degradation in nanoscale MOS transistors. With the tremendous increase in the cost and complexity of the fabrication, the modeling and simulations provide an alternative way to evaluate the performance of the transistors before going into the fab. Of course, this demands that the models used in the simulations have a predictive ability namely they must be able to model the device operation on the basis of a sound physics content, rather than by multiplying the number of fitting parameters. As a part of this work, we first extended the formulation of a nonlinear model for surface roughness scattering in planar transistors to account for matricial carrier screening, which is important in multigate devices. The model was then incorporated in an existing comprehensive Multisubband Monte Carlo simulator. This allowed us to analyze a wide range of planar structures from bulk devices to heterostructure devices. Motivated by the good results from the nonlinear model for planar devices, we developed a nonlinear model for surface roughness scattering for the 3D devices having fairly arbitrary cross-section shape, so as to analyze transistors without any approximation to their geometrical structure. This nonlinear surface roughness scattering model was then incorporated along with other important scattering mechanisms in a simulation framework largely extended and improved starting from the existing solver for Schrodinger-Poisson and 1D Boltzmann Transport Equation to analyze 3D FETs with arbitrary cross-section shape and biasing scheme. This simulation framework was then used extensively to calculate mobility values for silicon and InAs based multigate FETs having different cross-section shapes and areas. The simulator was then extended to account for the impact of self-heating and series resistance on the device characteristics, as they are known to significantly degrade the performance of the transistor. In order to simulate a complete transfer characteristic with all the scattering mechanisms, we developed a novel iteration scheme and a method to solve the Schrodinger equation adaptively to minimize the time needed in the simulation. The mobility analysis was then extended to a thorough comparison of different performance metrics. We have also benchmarked vertically stacked lateral nanowires (stacked NWs) against traditional FinFET, and simulations showed that surface roughness has a much stronger impact on the stacked NWs.
Oves Badami completed his Master's from IIT Bombay in 2013 with a CGPA 9.7. As part of his M.Tech. project, he developed a complete device simulator in which the electron transport was modeled ranging from semi-classical models to full quantum transport formulation. Subsequently, he worked at IBM SRDC Bangalore on FIELDAY development and at IIT Bombay as a Research Assistant on modeling of reliability in MOSFETs. Later he joined the PhD program at the University of Udine where he has recently submitted his PhD thesis. During the course of his PhD, we have developed a new model for surface roughness scattering in planar and 3D MOS transistors. He has also developed a comprehensive simulation framework along with adaptive algorithms to streamline the simulator. This was then used to benchmark different possible architectures for future CMOS technology nodes. He has published 11 papers in different conferences and peer-reviewed journals out of which 3 were in IEDM. He has also won the Best Paper Award at ESSDERC-2015 for developing tensorial screening formulation for new surface roughness scattering model.