Current systems place processor and memory dies inside packages, which allows them to be connected to the PCB and subsequently to other dies. A striking observation is that in the last two decades while silicon chips have dimensionally scaled by 1000X, packages on printed circuit boards (PCBs) have merely managed 4X. We make a case for packageless computing systems to cover this gap and its consequent impact on form factor, performance and power. Specifically, we use a novel integration technology Silicon Interconnect Fabric being developed at UCLA as the final assembly substrate and show that packageless computing can deliver 2X improvement in performance in addition to dramatically reducing system weight/form factor. In the second half of the talk, we show how the packageless assembly allows us to build waferscale computing systems with high yield. As a case study, we show that Waferscale GPUs can deliver over 18X performance and 140X EDP improvements over comparable package + PCB multi-GPU systems.
Puneet Gupta (SM’16) received the B.Tech. degree in electrical engineering from the Indian Institute of Technology Delhi, New Delhi, India, in 2000, and the Ph.D. degree from the University of California at San Diego, San Diego, CA, USA, in 2007. He is currently a Faculty Member with the Electrical and Computer Engineering Department, University of California at Los Angeles. He Co-Founded Blaze DFM Inc., Sunnyvale, CA, USA, in 2004 and served as its Product Architect until 2007. He has authored over 160 papers, 17 U.S. patents, a book and a book chapter in the areas of design-technology co-optimization as well as variability/reliability aware architectures. Dr. Gupta was a recipient of the NSF CAREER Award, the ACM/SIGDA Outstanding New Faculty Award, SRC Inventor Recognition Award, and the IBM Faculty Award. He led the multi-university IMPACT+ Center which focused on future semiconductor technologies.