Sparse system identification has received much attention in the last decade with many potential applications such as network echo cancelation, underwater acoustic communication, and high-definition television terrestrial transmission. There has been a flurry of research in this area with the invention of proportionate-type algorithms which are shown to outperform conventional LMS based algorithms for sparse system identification. However, not much is known about their optimized implementation in dedicated hardware because of the huge computational complexity. For achieving the best performance-complexity trade-off of the complex adaptive filtering algorithms, one has to focus on co-design of algorithm and architecture in an intertwined way rather than designing them in isolation. Several reformulations which substantially reduce the computational complexity of proportionate-type algorithms are discussed. Performance- complexity trade-offs associated with these reformulations, design aspects of the corresponding pipelined VLSI architectures and the application-specific integrated circuit (ASIC) implementation results will be presented.
Subrahmanyam Mula received the B.E. degree in electronics and communication engineering from Andhra University, Visakhapatnam, India, in 2001 and the M.Tech. and Ph.D. degrees in electronics and electrical communication engineering from IIT Kharagpur, Kharagpur, India, in 2003, and 2018 respectively. From 2003 to 2014, he was with Intel, Bengaluru, India, where he was involved in front-end design verification of gigabit Ethernet switches, processors, chip-sets, and GPUs. His current research interests include VLSI signal processing and adaptive systems.