SCL is India's only major silicon manufacturing facility. The speaker will talk about the following. · Developmental work presently going on in areas of CMOS ( Design, Process development, Test) · Developmental work in areas of MEMS ( in process, and planned) · Fab operation issues and requirements · Few areas of collaborative work ( particularly design of few IPs)
Mr. H.S. Jatana is Group Head of Design and Process at SCL. He was educated at BITS Pilani, and has worked at CMC, SCL, Rockwell Semiconductor and AMS Austria. He has worked in several areas of CMOS design and technology. He has been involved in the design of various ASIC products, and - with PGI Chandigarh - an anesthesia drug delivery system. His current interests are low-power CMOS design and process enhancements at the 180nm node. In particular, he has initiated new process development modules like HV, SOI, BiCMOS, CCD and III-V on Si. Mr. Jatana is also keenly interested in VLSI education and has conducted and participated in several conferences and workshops for the same.