Collecting, computing, and communicating information is becoming
inevitable in all spheres of human life. However, meeting the growing demand
of data at an affordable cost of energy is a big challenge. While
traditionally power dissipation in computation has contributed a significant
portion to the overall system power, with increasing date rates, energy
consumed for communication of data has become a major bottleneck for improving
system performance recently. As a result, recent research efforts have
primarily focused on improving energy efficiency of communication links.
Strategies like Dynamic Voltage and Frequency Scaling (DVFS) and Near
Threshold Voltage (NTV) operation help trading off performance (data rate) for
improved energy efficiency. However, many speed and data intensive
applications such as high performance servers or super computers require
lowest energy consumption at peak data rates, which is difficult to achieve
using DVFS or NTV operation.
In this talk, I will review the necessity for energy efficient data transfer and outline the challenges in improving energy efficiency of high-speed serial links. I will then present design techniques at both architecture- and circuit-level to overcome these challenges. I will also describe how the proposed techniques can be combined with DVFS and burst-mode operation to improve energy efficiency across a wide range of data rates. I will present experimental results obtained from prototype test chips to validate the proposed techniques. I will conclude with my plan for future research activities.
Saurabh Saxena is close to finishing PhD at University of Illinois at
Urbana-Champaign. His research is in clock generation circuits, high-speed
serial links, and delta-sigma modulators. He earned his bachelor’s and
master’s degree in electrical engineering at IIT Madras in 2009 under dual