Talk-1: High-k/metal gate stack technologies with EOT less than 0.5nm
In this talk, the importance of the continuous thinning of the gate oxide insulator even beyond 0.5 nm EOT is explained. The mechanism of the various problems for decreasing EOT below 0.5 nm is explained. The materials and processes to obtain sub-0.5 nm EOT Si-MOSFETs are introduced. Then, the current status of the high-k/metal gate stack MOSFET devices with EOT=0.5 nm and below are explained with benchmark of the published data. In addition with the high-k/metal gate stack technologies for Si-CMOS, those for III-V/Ge CMOS devices are also explained.
Talk-2: State of the art and future prospects for logic CMOS device technology In this talk, the importance of the effort to keep the downsizing trend for the logic CMOS devices for next 10 years is explained, considering the strong demands for low-power & high-performance logic devices in near future smart society in which so huge volume of data has to be handled. Then, current status of the state of the art 22 nm logic CMOS device technologies are introduced. The expected problems for the further downsizing are explained and technological solutions for the problems are shown. The limitation of the downsizing is discussed, followed by the introduction of the current status of several emerging device technologies aiming to replace the Si-CMOS logic devices.
Hiroshi Iwai received the B.E. and Ph.D. degrees in electrical engineering from the University of Tokyo and worked in the research and development of integrated circuit technology for 40 years. He worked in Toshiba for the 1st 25 years and moved to Tokyo Institute of Technology. He is now a professor of Frontier Research Center and Dept. of Electronics and Applied Physics, Interdisciplinary Graduate School of Science and Engineering, Tokyo Institute of Technology, Yokohama, Japan. Since joining Toshiba, he has developed several generations of high density static RAM's, dynamic RAM's and logic LSI's including CMOS, bipolar, and Bi-CMOS devices. He has also been engaged in research on device physics, process technologies, and T-CAD related to small-geometry MOSFETs and high speed bipolar transistors. He has authored and coauthored more than 700 international and 350 domestic journal/conference papers.
He has served on many committees of conferences and editors of journals, as well as a member of many evaluation committee of public organizations. For example, a member of IEEE Board of Directors, and IEEE Division 1 Director for 2010-11, the President of the IEEE Electron Devices Society, an elected member of the IEEE EDS AdCom, an editor of IEEE EDS Newsletter, a guest editor of IEEE Trans. on Electron Devices, and an editor of the Proceedings of many ECS Symposia. He has served as a visiting professor for Japanese, Chinese and Indian universities for many years, including that of D. H. Gandhi Distinguished Visiting Professor in IIT-Bombay.
His awards include Local Commendation for Invention from Japan Institute of Invention and Innovation (1990, 2005), Grand Prize of Nikkei BP Technology Awards (1994), IEEE EDS Paul Rappaport Award (1994), IEICE ES Electronics Award (1998), IEEE EDS J.J.Ebers Award (2001), and JSAP Award for the best paper (2002), IEEE BCTM Award (2007), Yamazaki-Teiichi Prize (2007), IEEE 2008 EDS Distinguished Service Award (2008), The Commendation for Science and Technology by the Minister of Education, Culture, Science and Technology, Prizes for Science and Technology, Development Category Award (2009).
His current research interests are Nano CMOS, Power MOSFET and Emerging Technologies: Si Nanowire MOSFETs, III-V MOSFETs, GaN Power MOSFETs, High-k gate insulator technology, Metal/silicide S/D technology.
Dr. Iwai is, a fellow of IEEE, a fellow of Institute of Electrical Engineers Japan, a fellow of the Japan Society Applied Physics, and a fellow of the Institute of Electronics, Information and Communication Engineers of Japan.