System on Chip (SoC) concept allows exciting opportunities for a wide range of hand held and mobile applications, including smart phones, high-end gaming consoles and tablet PCs. However, its implementation brings unique challenges, for example: low standby power, high packing density, high precision analog circuits, mixed signal design requirements, high voltage circuitry and related device enablement, integrated power amplifiers, electrostatic discharge (ESD) protection and self heating issues. In this talk we will look into three of these challenges, which are widely untouched in academia. These are ESD protection, high voltage device requirements and electrothermal modeling to handle self heating concerns. In the first part of this talk we will look into the advantages of drain extended MOS (DeMOS) devices and its importance for high voltage circuit requirements in modern SoCs. Circuits based on DeMOS devices can be found in high speed – high voltage interfaces (for. ex: USB3.0), power management units, level shifters, high voltage drivers and RF power amplifiers, working up to voltages of 3 – 20 volts. The second part of this talk will summarize various ESD events, required protection measures for modern SoCs and ESD behavior of DeMOS devices. ESD is known to be a critical stress event for semiconductor products, which can encounter during manufacturing, packaging, assembly and handling processes. Finally, the last part of this talk will summarize self heating concerns in nanoscale devices and theoretical framework required for electrothermal modeling. Moreover, recent investigations on the thermal failure of nano-scale devices under the normal operating condition will be presented.
Dr.Mayank Shrivastava received his B.Tech degree in Electronics & Comm from RGPV Bhopal in 2006, and PhD from IIT Bombay in 2010 in the area of Microelectronics. He worked as Senior Engineer with Infineon Technologies, USA and Intel Corp. (MCG), USA from Sep 2010 - Jan 2011, and Feb 2011 to Sep 2011, respectively. He was responsible for 28nm & 20nm ESD device and technology co-development, ESD device characterization, simulation and modeling topics at the IBM facilities in Essex Junction, VT and Hopewell Junction, NY, USA under the International Semiconductor Development Alliance. From Sep 2011 till date he has been working as Senior Engineer with Intel Corp. (MCG), Munich, Germany, where he has been responsible for 28nm ESD protection concepts and library development, 14nm ESD device and technology co-development, ESD device characterization, simulation and modeling topics.