Binary Decision Diagrams (BDD) have become state-of-the-art data structure in VLSI CAD. A special class of structurally synthesized BDDs (SSBDD) will be presented. SBDDs differ from "traditional" BDDs in the method of synthesis, having several dedicated properties, like one-to-one mapping between the SSBDD nodes and signal paths in the logic circuit. The last property makes SSBDDs very suitable for solving many test related problems where the traditional BDDs will fail. A motivation of introduction of SSBDDs will be presented along with a short overview about different applications in test generation, fault simulation, and multiple valued testing. A way to compress the model by introducing shared SSBDDs will be as well shortly discussed. High-Level DDs (HLDD) will b e presented as a generalization of BDDs for representing digital systems at Register Transfer and behavioral levels. An overview about definition of the model, synthesis of HLDDs, and applications for hierarchical test generation and high-level verification.
Raimund Ubar obtained his PhD in Computer Science from the Bauman Technical University of Moscow in Russia in 1971. He is currently a professor at Tallinn University of Technology and the head of Science excellence centre CEBE in Estonia. He is associated with about 25 universities in Europe. His research interests include digital test, design for testability, fault tolerance. Prof. Ubar is also a member of the Estonian Academy of Sciences and IEEE Computer Society Golden Core member.