In nanometer technologies, local interconnects are believed to cause major impact on timing and power in VLSI circuits. Just how large is the impact? This talk answers the question with results from a study carried out to assess the same in a quantitative manner on a real high performance design. The study shows that for RTL-to-layout synthesized (RLS) blocks, in a 45 nm technology microprocessor core, local interconnects contribute nearly 1/3rd each to the timing on the worst internal paths and to the dynamic power dissipation. This points to severity of the impact due to the local interconnects, which is likely to worsen with technology scaling. It also implies that algorithms/approaches underlying existing synthesis/physical design tools/methodologies have had limited success in mitigating the same.
Rupesh S. Shelar received PhD in Electrical Engineering from the University of Minnesota, Minneapolis in 2004. He was with Intel Corporation, USA from 2004 till 2012, where he contributed to Core i7 and Atom microprocessor designs in 45, 32, 22, 14 nm technologies in the areas of clock tree synthesis (CTS), global clock distribution, and interconnect impact analysis. He is a co-author of a book titled “Routing Congestion in VLSI Circuits:Estimation and Optimization” published by Springer in 2007. Currently, he is a principal engineer, responsible for physical design for SoCs, at LSI, Pune