His talk is a part of IBM Embedded Memory Workshop. Embedded memory is a key component in a wide variety of systems applications across computing infrastructure, telecommunication infrastructure, and consumer gadgets. By embedded memory here we specifically refer to those memory technologies that are tightly integrated with the processor logic such as SRAM, embedded DRAM, and 3D memory integration. In this workshop we will provide a tutorial overview of the key technology and design challenges that have shaped recent work in embedded memory. We will use examples from embedded memory development work at IBM to illustrate these challenges and their solutions. This workshop will be accessible to anyone with a basic background in semiconductor devices and circuit design. The talk may also be of interest to researchers and students working in allied areas such as microprocessor design and embedded systems.
Subramanian S. Iyer is IBM Fellow and Chief Technologist at the Microelectronics Division, IBM Systems & Technology Group, and is responsible for technology strategy and competitiveness, embedded memory and 3 Dimensional Integration. He obtained his Bachelor of Technology in Electrical Engineering at the Indian Institute of Technology, Bombay, and his M.S. and Ph.D. in Electrical Engineering at the University of California at Los Angeles. He joined the IBM T. J. Watson Research Center in 1981 and was manager of the Exploratory Structures and Devices Group till 1994, when he founded SiBond LLC to develop and manufacture Silicon-on-insulator materials. He has been with the IBM Microelectronics Division since 1997. Dr. Iyer has received two Corporate awards and four Outstanding Technical Achievement awards at IBM for the development of the Titanium Salicide process, the fabrication of the first SiGe Heterojunction Bipolar Transistor, the development of embedded DRAM technology and the development of eFUSE technology. His current technical interests and work lie in the area of 3-dimensional integration for memory sub-systems and the semiconductor roadmap at 22 nm and beyond. He holds over 40 patents and has received 22 Invention Plateau awards at IBM and is a Master Inventor. He received the Distinguished Alumnus award from the Indian Institute of Technology, Bombay in 2004. Dr. Iyer has authored over 150 articles in technical journals and several book chapters and co-edited a book on bonded SOI. He has served as an Adjunct Professor of Electrical Engineering at Columbia University, NY. Dr. Iyer is a Fellow of IEEE and a Distinguished Lecturer of the IEEE. In 2011 he received the Asian American Engineer of the Year ward. He is the recipient of the 2012 IEEE Daniel Noble medal for emerging technologies. In his spare time, he studies Sanskrit and role of Indic languages, traditions and culture in different parts of the world.