Our approaches to brain inspired computing today, rely on neural networks fashioned out of conventional von Neumann architectures. These tend to be energy inefficient compared to biological systems on account of bottlenecks to memory where the weights for the neural network are stored, modified and frequently accessed. This talk relies on two innovations: one is a device called the Charge Trap Transistor (CTT) – a High K gate CMOS transistor that can be used as an analog memory array to store and update weights; and method to scale such a neuromorphic system to brain-like scales with billions of intimately interconnected neurons. In this talk, we describe the physics of charge trapping in the Hi K bulk FINFET as well as partially depleted SOI devices and describe ways in which this effect can be used as an analog memory of adequate resolution for supervised and unsupervised learning as well as an inference engine similar to a memristor but with the advantage that it is a very conventional CMOS transistor and can be combined intimately with CMOS logic. Such array units can be cascaded into multiple levels of a deep neural network and this may be scaled up in two dimensions using a Silicon Interconnect Fabric (Si-IF) or in three dimensions using 3D Wafer-Scale Integration (3DWSI). We will describe the technologies as well as the processing and material challenges of these methods as well as some early experimental results.
Subramanian S. Iyer(Subu) is Distinguished Professor and holds the Charles P. Reames Endowed Chair in the Electrical Engineering Department and a joint appointment in the Materials Science and Engineering Department at the University of California at Los Angeles. He is Director of the Center for Heterogeneous Integration and Performance Scaling (CHIPS). Prior to that he was an IBM Fellow. His key technical contributions have been the development of the world’s first SiGe base HBT, Salicide, electrical fuses, embedded DRAM and 45nm technology node used to make the first generation of truly low power portable devices. He also was among the first to commercialize bonded SOI for CMOS applications through a start-up called SiBond LLC. He has published over 300 papers and holds over 70 patents. He was a Master Inventor at IBM. His current technical interests and work lie in the area of advanced packaging constructs for system-level scaling and new integration and computing paradigms as well as the long-term semiconductor and packaging roadmap for logic, memory and other devices. He has received several outstanding technical achievements and corporate awards at IBM. He is an IEEE Fellow, an APS Fellow and a Distinguished Lecturer of the IEEE EDS and EPS as well as it treasurer of EDS and a member of the Board of Governors of IEEE EPS. He is also a Fellow of the National Academy of Inventors. He is a Distinguished Alumnus of IIT Bombay and received the IEEE Daniel Noble Medal for emerging technologies in 2012.