An automated fault analysis approach, which can automatically characterize fault and subsequent relay operation is the focus of this presentation. It utilizes synchronized samples captured during transients from both ends of the transmission line to detect, classify and locate transmission line faults and also can verify that the tripped line indeed have experienced a fault. The proposed method is setting-free and transparent to fault resistance and different transmission line layouts, applicable to high resistance faults; detect, classify and locates fault with a very high accuracy while using moderate sampling rate for voltage and current measurement waveforms. The proposed method is tested for several faults simulated on IEEE 118 bus test system and it has been concluded that it can detect and classify a fault using pre and post fault recorded samples within ½ of nominal frequency cycle of fault inception and locate fault with 3% accuracy. This time response performance is highly desirable since with the increasing use of modern circuit breakers which can open the faulty line in less than two cycles, the time window of the captured waveforms is significantly reduced due to the unavailability of measurement signals after breakers open.
Papiya Dutta (S’08) received her Bachelor’s of Engineering in Electrical Engineering from Jadavpur University, India in 2003. She received MS (by research) degree from IIT Kharagpur, India in 2007. She received PhD degree from Texas A & M University, USA in 2014. Her research interests include fault location, substation automation, smart grid, plug-in hybrid vehicles, and evolutionary algorithms for optimization.