Spin waves are propagating disturbances in magnetically ordered materials, analogous to lattice waves in solid systems and are often described from a quasiparticle point of view as magnons. The attractive advantages of Joule-heat-free transmission of information, utilization of the phase of the wave as an additional degree of freedom and lower footprint area compared to conventional charge-based devices have made spin waves or magnon spintronics a promising candidate for beyond-CMOS wave-based computation. However, any practical realization of an all-magnon based computing system must undergo the essential steps of a careful selection of materials and satisfy the essential requirements of gain, concatenability, feedback prevention, logic function completeness and robustness with respect to thermal noise and variability. In this work, we identify suitable materials and propose a comprehensive scheme for developing an error-free clocked non-volatile spin wave logic device along with efficient transduction between spin and charge domain. Magneto-electric effect is used for efficient spin wave excitation, detection and non-volatile data storage (memory-inlogic). The proposed novel clocking scheme ensures non-reciprocity and sequential transmission of information. Overall, this work addresses a very critical question: “Can spin wave devices work in reality?” and provide a solid platform towards the practical realization of an error-free ultra-low power spin wave logic device.
SOURAV DUTTA received the B.E. degree in Electrical Engineering from Jadavpur University, Kolkata, India, in 2012. He is currently pursuing his Ph.D. degree in Electrical and Computer Engineering at Georgia Institute of Technology, Atlanta, GA, USA under Dr. Azad Naeemi. His primary area of research is modeling and simulation of Spintronic devices and interconnects for Beyond-CMOS application with special focus on spin waves which is funded by and in collaboration with Intel. From May to July 2016, he was a visiting researcher at IMEC, Belgium where he was involved in modeling and simulation of nanoscale plasmonic logic gates, magneto-plasmonics and spin-plasmonics for boolean and non-boolean computation for Beyond-CMOS application.