As CMOS technologies have shrunk to the scale of tens of nanometers, reliability and aging problems have emerged as a major challenge. These issues promise to grow increasingly troublesome in the future. There has been tremendous progress in developing new methods for modeling and diagnosing reliability at the level of individual transistors, but much less work on propagating these models to higher levels of abstraction to predict the reliability of larger circuits. This talk will provide a basic introduction to various circuit aging mechanisms and will then discuss research that develops computer-aided design techniques for estimating and enhancing the reliability of large digital circuits, with specific emphasis on failures due to phenomena such as bias temperature instability, gate oxide breakdown, and hot carrier injection, examining solutions that could practically be applied to analyze or improve the lifetime of a design.
Sachin Sapatnekar received his BTech from IIT Bombay in 1987, his MS from Syracuse University in 1989, and his PhD from the Univ. of Illinois at Urbana-Champaign in 1992. He is currently at the Univ. of Minnesota, where he holds the Distinguished McKnight University Professorship and the Henle Professorship in the ECE dept. He has been the Editor-in-Chief of the IEEE Transactions on CAD, the General Chair for the ACM/IEEE Design Automation Conference (DAC), and the Technical Program Co-Chair for the International Symposium on VLSI Design. He is a recipient of the NSF Career Award, six conference Best Paper Awards(3 at DAC, 1 each at ICCD, ISPD, and ISQED) and a Best Poster Award (IRPS). He has received the Semiconductor Research Corporation's Technical Excellence Award (2003), the Semiconductor Industry Association University Research Award (2013), and he is a Fellow of the IEEE. He was a Senior Fulbright Scholar at the Polytechnic University of Catalonia (UPC) in Spain in 2013, and is currently a D.J. Gandhi Visiting Professor at IIT Bombay.