A. N. Chandorkar

• Analog and Mixed signal VLSI Design
• Ultra-Thin Gate insulators for VLSI Technologies
• High-K Dielectrics for VLSI Technologies (Nano Electronics)
• RF VLSI Design
• Radiation Hard MOS Technologies
• Communication/DSP based System and chip Design
• Semiconductor Device modelling and Reliability Simulation Tools
• Memory Testing, Analog and Mixed signal Test and Fault simulation
• Accelerated Device Testing and Reliability,
• Modelling,High Power semiconductor Devices, Power Electronic Systems, Optically Switched Microwave components, Sensors
• Microelectronics System Packaging

• EE618 CMOS Analog VLSI Design
• EE668 System Design
• EE671 VLSI Design

• Ph.D. degree in Electrical Engineering, January 1978,University of Rajasthan, Jaipur. Thesis:'Influence of Schottky Barrier Injection on negative resistance Microwave Semiconductor Diode'.
• Research Work carried at CEERI, Pilani, Rajasthan. Research Supervisor: Dr. W.S.Khokle, Former Director, CEERI, Pilani.
• Master of Science Technology, in Electronics Engineering, 1969. Thesis:'Study of TTL Logic Circuits', Supervisor: Prof. K.V. Ramanathan

• Professor, Department of Electrical Engineering, Indian Institute of Technology, Bombay, From February 1988 till Today

• Associate Professor, Department of Electrical Engineering, IIT Bombay from June 86 to 1988.

• Assistant Professor, Department of Electrical Engineering, IIT Bombay from April 83 to June 86

• Research Scientist, Solid State Electronics Group and Microwave Group of Tata Institute of Fundamental Research, Mumbai, From 1978 to 1983

• Research Engineer, Advanced Centre for Electronics Systems, Department of Electrical Engineering, Indian Institute of Technology, Kanpur From 1974 to 1978.

• Research Associate, Department of Electrical Engineering, Indian Institute of Technology, Madras, From Jan. 1974 to April 1974

• Senior Research Fellow, Solid State Devices Group, CEERI, Pilani, (with Dr. Amarjit Singh, then Director, CEERI), From 1970 to 1974

• IIT Bombay's most prestigious award for EXCELLENCE in TEACHING, for the year 1999
• IETE’s 6th SVC Aiyya award for “Motivating Research in Microelectronic Devices for past 10 years, Year 2000.
• Fellow of Institution of Electronics and Telecommunication Engineers,New Delhi, India. Year 2000.
• Vice-Chairman, International Society of Reliability Engineers, Bombay Chapter.
• Member, IEEE, (USA)
• Fellow, Maharashtra Academy of Sciences.2003 Member, Faculty of Technology, University of Mumbai (3year term)
• Was invited by Mayor of City of Kitakyushu, Japan to present an Invited paper in the Second “Asian University Workshop on Semiconductor Design”in December 2003. Was India’s representative and the out come of this Workshop is that we can now have collaboration on projects and students exchange program be started between IIT Bombay and University if Kitakyushu, University of Waseda and Kyushu University at Fukokova. This conference was follow up of the first similar conference in January 2003, which was also attended by him as Mayor’s guest.

• “Design of RF Tuner for Cable Modem applications' paper authored by A. N. Chandorkar, Veeresh Babu and Sumantra Seth was adjudged as A.K.Choudhary Best paper in the 17th International Conference on VLSI DESIGN, 2004 recently held in MUMBAI. This award carries a citation and Rs 10000/- as cash prize.

• I am currently holding following positions in the Institute
  • Head of Advanced Centre for Research in Electronics
  • Convenor of Inter Disciplinary Program in Reliability Engineering.
  • Convener, GG Lecture hall Complex building Task-Force
  • Co-Coordinator, VLSI SMDT project
  • Member, Institute Master Plan committee
  • Member, Joint Consultative Committee
  • Member, AC and fixtures Committee
  • Member Senate Search Committee (2003 onwards)
  • Member Senate committee for looking into working of Interdisciplinary Programs and Non-Teaching Centres.

• Head of the Department of Electrical Engineering at IIT Bombay, Mumbai,From September 1994 to October 1997.The Dept. has around 40 Faculty Members, 100 Technical Staff and 600students.
• Member PGAPEC (1986- 1990)
• Member DPGC of EE department (1986-1989)
• Member Furniture committee (1995-2001)
• Member Institute Search Committee (1999-2000)
• Associate and later warden Hostel no 3 (1986 to 1989)

• Industry -Interaction upgraded
• Enhanced No of Sponsored Projects were received by the Department
• A New Dual -Degree Program in Electrical Engg. Started.
• Review of B.Tech curriculum and up gradation.
• Conceived and organised first Student's all India level Technical Festival called TECHFEST
• Department - Building’s renovation and Rehabilitation
• Texas Instruments, USA and INTEL, USA were convinced of setting of Two Laboratories in the Department.
  • TI DSP Laboratory: Equipment and Software worth 36000 US Dollars was provided.
  • INTEL MICROELECTRONICS Laboratory: Intel Pentium-II Machines, A Server Machine and Software worth 150000 US Dollars was provided.

• Multi National companies like Texas Instrument (India), Cypress (India), Arcus (India), Silicon Automation Systems (India) and Siemens (India) agreed to provide sponsorship for M.Tech. Fellowship Program in Microelectronics.
• AICTE sponsored Industry - Academic Institutions Partnership Workshop was organised . 50 senior managers from Mumbai, Pune, Nashik, Delhi, Bangalore and Chennai from Electronics Industries along with 50 faculty members from various academic institutions including those from IIT Bombay participated. The Workshop has resulted in increased interaction of EE Dept of IIT Bombay with Industries like Crompton Greaves, Texas Instruments, Semiconductor Complex, Cypress Semiconductors, BSES Mumbai, MECO Instruments and others.

• Technology Mission Project: Supervised a Technology Mission Project sponsored by Planning Commission of Govt. of India.( 1996-1999 ). The project is joint venture between EE Dept., IIT Bombay and M/S Crompton and Greaves Ltd for Development of two kinds of Fractional Horse Power Motors using Permanent Magnets. These motors have been designed and some Proto-types have been fabricated by Crompton Greaves.The total Budget outlay is of Rs. 88.00 Lakhs of which Planning Commission has contributed Rs .68.0/-Lakhs and balance of Rs. 20/-Lakhs is provided by M/S Crompton and Greaves Ltd. Five Faculty Members and 4 Mission Engineers were involved in this Project from IIT side and a Team led by Vice-President from the Industry side.
• Continuing Education Programs: Conducted both INHOUSE and on Campus Short -Term (2days to 45 days). Courses for Industries in the areas of VLSI Design and Technology, System. Hardware and Reliability, Power Electronics for the last 15 years. Particularly In-house programs for Railways at Nashik (IREEN) is being continued for last 10 years under my Co-ordinatorship in the area of Power Electronics. Other Industries include BEL Bangalore, S.G.S. Thomson, Noida, and Semiconductor Complex ,Chandigarh. , where VLSI Design Courses were conducted. Also currently participating in In-house 3 years certification program for Chemical Engineering at Reliance Industries, Patalganga, Near Navi Mumbai. Recently CEP course was conducted at IIT campus on “ Basics of Analog VLSI Design. This was open course with the help from EDA company Cadence (India)
• Negotiated a joint Research Project with Seimens A.G., Germany, University of Bundewehr, Munich: Germany and IIT Bombay for Study of Ultra Small Channel MOS Devices. Siemens will support two Research Scholars A.G., Germany

• My team of colleagues successfully carried out following projects under my leadership:
  • Automated X-Rays collimator for Seimens Ltd.(Rs 50000/-)
  • Hardness Tester for Galaxy Industries (Rs. 20000/-)
  • Energy Supervisor for MECO Instruments, Mumbai (Rs.150000/-)
  • Call logger for Communication Centre for System Enterprises. (Rs.20000/-)
  • Semiconductor Complex Ltd for Chip Design Verification (Rs5000/-)
  • Controlnet, Goa: Analog PHY Design for Networking. This project has resulted in first Analog chip successfully fabricated in first run itself.(Rs 300000/-). I was acting as Retainer for yearlong project.
  • Consulted on One and half year student collaborated Projects with companies like SASKEN Communication Technologies, Texas Instruments (INDIA), Cypress Semiconductors (India), and National Semiconductor (India).These projects were on state of the art VLSI Design issues which companies are currently working on for their Products. E.g. An Analog Version of very Fast Viterbi Decoder is currently under investigation.
  • Consulted on EDA development for CAM and Dual port memories for Synplicity EDA Software Company (USA) at Bangalore in 2003.
  • Consulted QualCore Logic Ltd. Hyderabad ,2004. The consultation is for development of design of Power Meter chip which uses Sigma-delta Modulation technique.
  • I was consulted by Silicon Automation Systems ltd. Bangalore (Now known as SASKEN Communication Ltd.) as Consultant for their VLSI DESIGN activities for 2 Years (1997-1999).
  • I am been consulted by QualCore Logic Ltd., Hyderabad for their Mixed signal design project (2004)

Worked for large number of Govt. Agencies’ Sponsored Projects in last 25 years. In some of them I was Principal Investigator and in others I was Investigator. The agencies include Department of Electronics, Department of Defence, M.H.R.D. ,and Department of Atomic Energy. The List, which follows, now gives salient features of the Projects:

• Centre for Microelectronics - Sponsored by M.H.R.D. (1985-1995): Total outlay Rs. 17.5 Million. I was Principal Investigator for the project from 1990 to 1995.Prof. J.Vasi and Prof. R. Lal were the other two Investigators. Prof. J.Vasi was Principal Investigator from 1985 till 1990. Major task was to set up 3 micron NMOS Fabrication Facility and promote Teaching and Research in area of Microelectronics. Designed and Fabricated a 5 micron Gate-Array Chip in the lab which has Class 1000 Clean Room and large no. of Characterisation Set-ups
• Radiation Effects on MOS Devices- Sponsored by Dept. of Electronics for the period of 6 years from 1988 till 1994. I was Principal Investigator of this Project along with Prof Vasi and Prof. Lal. Total Outlay of Rs. 10.3 Millions. This project has been most successful project of our Group and we received International Visibility for our Efforts. We have successfully developed RADHARD MOS Technology particularly for MOS Insulators and showed a working NMOS IC chip Radhard for 1 Megarad of High Energy Gamma Radiation. Currently efforts are on to transfer the know-how to ITI Bangalore
• Radiation Effects Modelling and Circuit Simulation: Sponsored by DRDO for the outlay of Rs.2.25 Million (1992 to 1994) I was the Principal Investigator for this project. In this project we developed Radhard Circuit Simulator called RADSPICE. Other Investigators were Prof. J. Vasi and Prof D.K.Sharma and Prof.A.Das.
• Accelerated Test strategy for components and Devices: Sponsored by Board of Research in Nuclear Sciences (DAE) for three year period from 1997 with outlay Rs. 1.25 million with myself as Principal Investigator Test set-ups for Accelerated Testing under Temperature and Humidity stressing for components is complete so far.
• Design and Fabrication of 94 GHz SPST Switch using PIN Diodes: The project was joint venture between SSPL, Delhi; SAMEER, Bombay and IIT Bombay and is sponsored by DRDO .The Switch will be Front-End of the NAG Missile. The total outlay of the Project is Rs. 18.0Million of which our share is only of Rs. 20/- lakhs .Our task was to Design PIN diode array structure with Full Process Design. This task had been completed by us ,and SPL has just succeeded in Fabricating Four Modules SPST switch based on our design and all of them show all the desired characteristics at 94 GHz. Prof. D.K. Sharma was other Investigator from our side.
• Mixed Signal Chip Design: Sponsored by M.H.R.D. for two year Period from 1998 March for outlay Rs.9.0 Lakhs. I was the Principal Investigator for this Project.
• National Process Simulator: Sponsored by Dept. of Electronics. Completed in 1990. Total outlay of Rs 3.5 Lakhs. I was one of the Investigators.
• VLSI Design Centre: Sponsored by Dept .of Electronics in 1988 and still supported by them. Total initial outlay was Rs. 7.5 Million. I am one of the major Investigators of this Project. VTI and CADENCE tools with SUN platforms have been installed for VLSI chip Design. I along with number of students carried out Chip Designs for number Digital Systems and of late Analog Systems.
• VLSI IMPACT project (SMDT Project): Sponsored by Ministry of Information technology for Training to Engineering college Teachers in the area of VLSI Design. Total outlay is Rs. 9.5 million and has started now. I am the Co-Coordinator of the Project along with Prof SSSP Rao of CSE Dept
• Neutron Radiation Effects on MOS Devices: Sponsored by B.R.N.S. (DAE) for outlay of 19.5 Lakhs.for period of three years Starting from 1997.Prof. D.K. Sharma is Principal Investigator and myself along with Prof. J.Vasi, Prof RLal were Investigators.
• C-Band Phase Shifter design and fabrication: Sponsored by DRDO at ACES, IIT Kanpur. As an Investigator I had designed and fabricated PIN diodes for the Phase Shifters.(1974-1978)
• X-Band Mixer Diodes: Sponsored by DRDO for Emergency Replacement of Mixer Diodes of equivalent specs of 1N23E in old Russian made RADAR at Balasore. Schottky Barrier diodes were designed and fabricated in record time of SIX months at SSE and Microwave Group of TIFR, Mumbai. I was the major investigator in Device design and fabrication.
• High Voltage PIN Diodes for Phased Array Radar: Project sponsored by Dept. of Electronics through NRC for outlay of Rs. 18.0 Lakhs at TIFR. Principal Investigator was Dr.B.K.Sarkar however I was responsible for design and complete processing of PIN diodes for X-Band operation . Successfully fabricated 1800-volt PIN diodes.
• Development of 5-Micron CMOS Metal Gate Technology: At Solid State Electronics Group of Tata Institute of Fundamental Research, Semiconductor Complex Ltd was initiated and I was one of the members of Technical Team which successfully fabricated First CMOS Chip under guidance of Prof. K.V.Ramanathan. My major contribution was in developing a New Pyrogenic System for growth of low oxide charge Field- Oxide. I also standardised HCL grown Gate Oxide technology then.
• VLSI Impact project Phase II: Sponsored by Ministry of Information Technology for development of CAD tools for VLSI Designs.I am the Co- Coordinator of the Project along with Prof SSSP Rao of CSE Dept.
• MHRD sponsored project on “ Development of expertise in Microelectronics System Packaging”. Total outlay is around Rs 7.0 Crore per Institute. I am the designated Principal Investigator for the Project.

Acted / Acting as Expert Member on following committees:

• Member Reliability Committee of Atomic Energy Regulatory Board (since97).
• Member Board of Research Nuclear Sciences Advisory Committee on Electronics and Instrumentation (1993-1998)
• Member of various Advisory Committees and Selection Committees of SAMEER, IIT, Bombay Campus.
• Member Advisory Committee of M.H.RD (Govt. of India) on Project sanctions and Evaluation ( 1987-1992)to various Engineering Institutions including IITs.
• Member DSIR ‘s committee on award of R&D status to Industries.
• Member DSIR’s committee on selection of the Best Industry of the year in the area of Electrical Engg.(1997-1998)
• Member Evaluation Committees of Dept. Electronics (Govt. of India) for the projects in the area of Microelectronics.
• Member various Selection Committees of CEERI Pilani for selection and promotion of Scientists uptoE2 level (1988-1994)(9) Member Maharashtra Public Service Commission’s Selection committee for Professors /Asst. Professors in Govt. Engg. Colleges of Maharashtra
• Member UPSC ‘s Selection Committees in area of Electronics Engg.
• Member Selection Committees for Academic Institutions of Engineering for Faculty positions as organised by Director of Technical Education,Maharashtra.(Since1992)
• Member Committee for Engineers Recruitment in State Bank of India and other Nationalised Banks (Since 1994)
• Member Selection Committee of VSNL, Mumbai for recruitment of Senior Engineers (since1995)
• Member Selection Committees of DTSR for promotional Interviews of Scientists of Defence Laboratories.
• Member Executive Committee, SAMEER, IIT campus, Powai.

Invited Technical Papers, Talks, and Chairmanship in Conferences:

• I held the position of General –Chair for “17th International Conference on VLSI DESIGN and 3rd International Conference on Embedded System design” which was held in Mumbai from 5th to 9th January 2004. This Conference is India’s most prestigious VLSI conference and this time around 750 delegates attended it from countries like USA, Europe, Japan and India. There were 5 plenary talks, 2 Banquet Speeches,32 Invited talks by most eminent researchers from Academia and VLSI industries. There were 92 Contributory papers and 45 Poster papers to make this conference most representative VLSI conference in Asia.

• I was Organising committee Co-Chairman and Program Committee Chairperson for the National Seminar on “ VLSI Systems, Design And Technology-2000” organised at IIT Bombay from 9th to 12th December 2000.Some 400 persons from various VLSI industries and academicians attended the seminar.

Recent Invited Talks in International Institutions:

• “MOS Dielectrics for ULSI”: Frontier Collaborative Research Centre, Tokyo Institute of Technology, Yokohama, Japan, 2003.
• “Ultrathin Insulators: Growth and Characterization,Department of Electrical Engineering National University of Singapore, 2003
• “ Low voltage Analog Circuit Design,Institute of High Performance Computing, Singapore, 2003
• “ Microelectronics at IIT Bombay and modelling issues in Deep Submicron Devices”, Semiconductor Technology Academic Research Centre (STARC),Yokohama, Japan, 2003
• “System on Chip Design activities” , 2nd Asian University Workshop on Semiconductor Design” Kitakushu, Japan Dec. 2003.

(Local popular lectures on VLSI Design and Technology

• Invited Lectures on Advances in VLSI were delivered at various Institutions in India like:IETE Nagpur section, SGSITS -Indore, V.E.S.I.T., Mumbai, DM college-New Bombay, R.A.I.T.-New Bombay, Fr Rodriguez College-New Bombay,IETE Bombay section,Thadomal Shahni College of Engineering-Mumbai.

Department of Electrical Engineering
IIT Bombay, Powai
Mumbai 400 076, India
Email : anc[AT]ee.iitb.ac.in
Phone (Internal(O)) : (0091 22) - 2576 7441
Phone (Internal(R)) : 8441
Office room no: EE 132
Fax: (0091 22) - 25723707

Publications in Conferences and Journals

• Veeresh Babu, Sumantra Seth and A.N.Chandorkar,“Design of RF Tuner for Cable Modem application”,Proc. 17th International Conference on VLSI Design, 7th to 9th January 2004,Mumbai, India.
• Srinjoy Mitra and A.N.Chandorkar, Design of Rail-to-Rail CMR with 1Volt Supply, Proc. 17th International Conference on VLSI Design, 7th to 9th January 2004,Mumbai, India.
• Rajeshwar Sable, Ravi Saraf, R. Parekhji and A.N.Chandorkar BIST technique for Selective detection of NPSFs in Memories,(Poster paper). Proc. 17th International Conference on VLSI Design, 7th to 9th January 2004,Mumbai, India.
• S.J.Vaidya, D.G.Borse, D.K.Sharma and A.N.Chandorkar.Isochronal Annealing Effects on Neutron Radiation Induced Trapped charge”Proc of 10th International Symposium on the Physical and Failure Analysis of Integrated Circuits, Singapore, July 2003
• S.J.Vaidya, D.K.Sharma, A.M.Shaikh and A.N.Chandorkar, ” Neutron Induced Degradation in Nitrided Pyrogenic Field Oxide MOS Capacitors“, Nuclear Instruments and Methods in Physics Research B, 194, pp311-318, 2003
• Ravi Saraf, R. Parekhji and A.N.Chandorkar, “Architecture for Programmable Memory BIST, VLSI Design And Test Workshops 2001, Bangalore, August 16-18, 2001.
• S.R.Shevgaonkar, A.N.Chandorkar and Dinesh Sharma,” Optically Controlled Microwave Phase shifter using Mach-Zender Interferometer Geometry, Microwave and Optical Technology Lett.28, pp15-21, 2001.
• S.R.Shevgaonkar, A.N.Chandorkar and D.K.Sharma,”Microwave Transfer through an optically excited microstrip gap”, Proc. Symp. On Advances in Microwave and Light wave Tech.pp239-242, 1998.
• S.R.Shevgaonkar, A.N.Chandorkar and D.K.Sharma,”Analysis of cylindrical Semiconductor Antenna”, Proc. International Conference on Computers and Devices for Communications, CODEC-98, pp53-56, 1998
• S.R.Shevgaonkar, A.N.Chandorkar and D.K.Sharma,”Analysis of photo-induced Semiconductor Antenna”, PHOTONICS-98, pp223-226, 1998.
• D.G.Borse, S.J. Vaidya and A.N.Chandorkar,” Study of interface trap generation due to high field stressing and its temperature dependence in 2.2 nm Gate Dielectrics”, IEEE Trans. Electron Devices, vol.49( no.4) April 2002 .
• D.G.Borse, Manjula Rani K.N., A.N.Chandorkar, J.Vasi, V.Ramgopal Rao, B.Cheng, and J.C.S Woo.,” Optimisation and Realization of sub 100nm channel Length lateral Asymmetric p-MOSFETs”, IEEE Trans. Electron Devices, vol. 49(no.6), June 2002
• D.G.Borse, S.J.Vaidya and A.N.Chandorkar, ”Comparison of 4 nm Gate Dielectrics Grown in O2 and N2O ambient on the basis of SLIC and Interface State generation due to Field stressing” Proceedings of International Conference on Communications, Computers and Devices (ICCCD-2000)”IIT Kharagpur,vol.1, pp257-260, Dec.2000.
• D.G. Borse, S.J.Vaidya and A.N.Chandorkar, “Study of high quality Ultra thin Oxides for scaled MOS devices from Reliability point of view” Proc. of National Seminar on VLSI System, Design and Technology (VSDT-2000),pp24-27,Dec.2000.
• D.G.Borse, S.J.Vaidya, and A.N.Chandorkar, “Comparison of 4 nm.dry and N2O Grown Gate dielectrics from reliability point of view”, 43rd DAE Solid State Physics Symposium, Mumbai, Dec.2000.
• Pallavi Krishnamurthy, A N Chandorkar, “Growth and study of High-K Ta2O5 Films Deposited by Ta Sputtering Followed By its Thermal Oxidation, Proceedings of the Eleventh International Workshop on the Physics Semiconductor Devices, 2001, Vol2, pp.1307-1309.
• Pallavi Krishnamurthy, and A N Chandorkar, “Reliability studies of 100 nm. Ta2O5 films, used as high-K dielectric in MOS Devices with and without nitridation in NH3, Proc.of the International conference on Micro and Nano Engineering, 2001. Grenoble, France, pp1307-1309
• Pallavi Krishnamurthy and A. N. Chandorkar, “Ta2O5: A Potential Candidate for future DRAM generations in VLSI”, Proceedings of National Conference on Advanced Computing, 2002. pp.23-27.
• S.J.Vaidya, B.G.Tiwari, D.G.Borse, A.N.Chandorkar, D.K.Sharma, and A.M.Shaikh, Neutron Irradiation Effects on Nitrided Pyrogenic Field Oxide”, 43rd Department of Atomic Energy Solid State Physics Symposium 2000, December 2000.
• S.J.Vaidya, B.G.Tiwari, D.G.Borse, A.N.Chandorkar, D.K.Sharma, and A.M.Shaikh, “ Non –Ionising radiation effects on MOS structures, International Conference on Communications, Computing and Devices (ICCCD-2000), pp 163-165, December 2000.
• M.Y.Joshi, B.K.Sarkar and A.N.Chandorkar, “ Design and fabrication of Microwave Resonator using Cr.-Au film on Al2O3 substrate and HTSC Film on LaAl2O3 substrate and their comparison, International Conference on Communications, Computing and Devices (ICCCD-2000), pp 337-339, December 2000.
• A.N.Chandorkar and Yogesh J.Pitkar,” MOSFET Reliability Simulation using Fast Timing Simulator ILLIAD”, Proc. of the International Conference on Quality, Reliability and Control (ICQRC-2001), Mumbai, Dec.2001.
• Anil Thosar and A.N.Chandorkar,”Combined effect of Temperature and Humidity on Thin SiO2 films”, Proc. of the International Conference on Quality, Reliability and Control (ICQRC-2001), Mumbai, Dec.2001.
• K.T.Oomman Tharkan, A.N.Chandorkar and S.S.S.P.Rao,”Development of an abstract model for Non-volatile Static Random Access Memory”, Defence Science Journal, December 2003

Earlier Publications till 1997

• R.M. Vadjikar, A.Nath, and A.N.Chandorkar,”Growth and Formation Model of Porous Silicon”, Nanostructures Materials vol.8,173,(1997)
• Ranjeet Ranade, Sanjay Bhandari and A.N. Chandorkar, “VLSI Implementation of Artificial Neural Network Based Digital Multiplier and Adder,” Proc. 9th International Conference on VLSI Design, Bangalore, India, (1996)
• B.M. Deb and A.N. Chandorkar, Theory of hopping transport of holes in amorphous SiO2,” J. Appl. Phys. 77, 5248 (1995)
• B.M.Deb and A.A. Diwan and A.N.Chandorkar, “Quantum Mechanical transport of holes in Silicon Dioxide”, Proc. of the Eighth International Workshop on Semiconductor Devices, New Delhi (1995)
• R.M.Vadjikar, A.N.Chandorkar and D.K.Sharma,”Diffusion limited Aggregation Model application to Porous Silicon Growth,” Nanostructures Materials, vol.5,273,(1995)
• A. Mallik, A.N. Chandorkar and J. Vasi, “Capture cross-section of hole traps in Reoxidized nitrided oxide measured by irradiation,” Solid - State Electronics 38, 1851 (1995)
• S.S. Moharir, A.N. Chandorkar and J. Vasi, “Data and Modelling of HCl Oxidation of Silicon,” Journal of the Institution of Engineering (India) 76, 2 (1995)
• A. Shanware, N. Godambe, J. Vasi, A.N. Chandorkar and A.Das, “Modelling and Characterisation of Commercial CMOS IC’s Under Radiation,” Proc. of the Eighth International Workshop on Physics of Semiconductor Devices, New Delhi (1995)
• R.M.Vadjikar, R.M.Nandedkar, D.D.Bhawalkar.R.Dussane, and A.N.Chandorkar Fabrication and Study of Porous Silicon morphology by SEM techniques, J.Material Science Letters, vol. 13.222,(1994)
• R.M.Vadjikar, B.Jain, D.D.Bhawalkar, R.V.Nandedkar, R.Sriniwasa, and A.N.Chandorkar, “Effects of Chemical Treatment in HF and NH4F solutions on Photoluminescence of Porous Silicon,” Material Science and Engineering B,Vol.23, L13,(1994)
• A. Mallik, J. Vasi and A.N. Chandorkar, “A Study of Radiation Effects on Reoxidized Nitrided Oxide MOSFETs, Including Effects on Mobility, Solid State Electron, 36,1359 (1993)
• A. Mallik, J. Vasi and A.N. Chandorkar, “The nature of the hole traps in Reoxidized nitrided oxide gate dielectrics,” J. Appl. Phys. 74, 2665 (1993)
• A. Mallik, J. Vasi and A.N. Chandorkar, “Electron Trapping during Irradiation in Reoxidized Nitrided Oxide,” IEEE Trans. Nucl. Sci. NS-40, 1380 (1993)
• A. Mallik, J. Vasi and A.N. Chandorkar, “Hole traps in RNO gate dielectrics,”Proc. of the Seventh International Workshop on the Physics of Semiconductor Devices, New Delhi (1993).
• A. Mallik, V. Ramgopal Rao, A.N. Chandorkar and J. Vasi, “Trap generation upon Irradiation in RNO gate dielectrics,” Proc. of the Seventh International Workshop on the Physics of Semiconductor Devices, New Delhi (1993)
• A. Mallik, A.N. Chandorkar and J. Vasi, “Electron trapping in RNO during irradiation, 30th IEEE Nuclear and Space Radiation Effects Conference, Snowbird, USA(1993)
• A.J.Choksi, R.Lal, and A.N.Chandorkar,” Electrical Properties of Silicon Dioxide Films grown by Inductively coupled R.F.Plasma Anodisation”, Solid State Electronics, vol34, No. 7,765,(1991).
• S.V. Kolluri, A.N. Chandorkar and A. Dhaul, “Indium Doping of Silicon Using an Evaporated Indium Film,” J. Vac. Sci. Technology (1993)
• V.A. Surlekar, U.B. Desai and A.N. Chandorkar, “VLSI Implementation of FIR Digital Filter using Residue Number System Arithmetic,” Texas Instruments Technical Journal, Vol9, No 4, 47 (1992)
• A.N. Chandorkar, A.J. Choksi and C. Elizabeth, “Influence of RF Plasma Anneal on Dry and Pyrogenic oxides under radiation,” Proc. of 23rd IEEE Semiconductor Interface Specialist Conference, San Diego, USA, (1992)
• K.Ramesh, A.Agarwal, A.N.Chandorkar, and J.Vasi,”Role of Electron Traps in the Radiation Hardness of Thermally Nitrided Silicon Dioxide,” IEEE Electron Device Lett.,Vol.12,No.12,(1991)
• R.M. Patrikar, A.Mallik, L.Vijayraghvan, R.Lal. A.N.Chandorkar, “Flat band Voltage shift due to Irradiation of Pyrogenic Oxide,” Proc. of the Sixth International Workshop on Semiconductor Devices, New Delhi (1991)
• A.J.Choksi, R.Lal, and A.N.Chandorkar,” Electrical Properties of Silicon Dioxide Films grown by Inductively coupled R.F.Plasma Anodisation” ,Solid State Electronics, vol34, No. 7,765,(1991).
• M.H.Madhusudan Reddy, S.R.Jawalekar, and A.N.Chandorkar, “Analogy between Electrical and Structural properties of Electron -Beam deposited SnO2“,Thin Solid Films, 187,171.(1990)
• M.Madhusudan Reddy, S.R.Jawalekar, and A.N.Chandorkar, “The Effects of Heat treatment on the Structural Properties of Electron - Beam Evaporated SnO2 Films” , Thin Solid Films, 169,117,(1989)
• K.Ramesh, A.N.Chandorkar, and J.Vasi,”Study of Traps in Silicon Dioxide due to Mobile Sodium Ions at the Si -SiO2 Interface,” J.I.E.T.E., Vol.33, No.1,(1987)
• Urvish Medh, A.N. Chandorkar and J.M. Vasi, “Some Development in Systolic Structures,” CAD Workshop at SCL, Chandigarh,(1985)
• Anant Adke, A.N. Chandorkar, P.S. Subramanian and S.S.S.P. Rao, “Placement and User Interface for a Gate Array design system,” Workshop on CAD at SCL, Chandigarh, (1985)
• Jitendra Apte, A.N. Chandorkar, P.S. Subramniam and S.S.S.P. Rao,Hierarchical Gate-Array Router,” Workshop on CAD at SCL, Chandigarh, (1985)
• Sudha V. Kolluri, A.N. Chandorkar and Prakash R. Apte, “Studies of Indium doping for Infra-red Sensors,” III rd International Workshop an Physics of Semiconductor Devices I.I.T. Madras, (1985)
• K. Ramesh, A.N. Chandorkar, J.M. Vasi, “Study of Sodium - related Electron Traps in SiO2 by B-T Stressing,” III rd International Workshop an Physics of Semiconductor Devices, I.I.T. Madras, (1985)
• A.N. Chandorkar, V.T. Karulkar and K.V. Ramanathan, “Dependence of Partial Pressure on Pyrogenics Growth of Silicon Dioxide,J.Elect.Chem.Soc.2, P 415(1985)
• A.N. Chandorkar, A.S. Vengurlekar and K.V. Ramanathan, “X-Ray Photoelectron Spectroscopy Study of Chlorine Incorporation in Thermally Grown HCl Oxides on Silicon,” Thin Solid Films, 114, 285, (1984)
• A.S. Vengurlekar, A.N. Chandorkar and K.V. Ramanathan, “MOS C-V Characteristics and dielectric properties of Ion - Implanted Thermal Oxides on Silicon”, Phy. Stat. Solidi (a), 81, (1984)
• A.N. Chandorkar, V.T. Karulkar and D.K. Sharma, “Anomalous behaviour of VLSI compatible Thin Silicon dioxide Films,” II nd International Workshop on Physics of Semiconductor Devices, New Delhi, (1983)
• A.N. Chandorkar, Avinash Joshi and S. Pai, “Study and Growth of Phosphorous doped oxides as diffusion source,” Silver Jubilee Symposium on Electronics and Communication in 80’s, I.I.T. Bombay, (1983)
• A.N. Chandorkar and V.T. Karulkar, “Study and Growth of Pyrogenic oxides for CMOS Technology,” I st International Conference on Physics of Semiconductor Devices, New Delhi, (1981)
• A.N. Chandorkar and Prakash R. Apte, “On Life - time Characteristics in PIN diodes,” International Symposium on Microwaves and Communication, I.I.T. Kharagpur,(1981)
• A.N. Chandorkar and Prakash R. Apte, Fabrication of 2000 V. PIN diode,”International Symposium on Microwaves and Communications, I.I.T. Kharagpur,(1981)
• A.N. Chandorkar, Prakash R. Apte and M.C. Kumar, “Self Aligned Schottky Barrier diode fabrication using Lift - off Technique,” DAE Symposium, Hyderabad, (1980)
• A.N. Chandorkar and M.M. Hasan, “Fabrication of transmission lines in Silicon for Monolithic microwave integrated circuits,” IETE Symposium,Nov 1978, New Delhi.
• P.S. Bhatnagar and A.N. Chandorkar, “Radiation resistance of Dipole Antenna with an unsymmetrical displaced feed points by method of moments,” J. Inst. Engg., Vol. 36, ET-2, Dec. 1975
• P.S. Bhatnagar and A.N. Chandorkar, “Method of moments for radiation Resistances of Non-linear dipole antennas having transversally displaced feed oints,” J.I.E.R.E., 24 March, 1975.
• B.R. Singh, A.N. Chandorkar and B.R. Marathe, “Surface State Distribution and Ion Migration in Thermally Grown Silicon Dioxide Films,” Biannual Conference of Electrochemical Society (U.S.A.) at Sanfransisco (U.S.A.), (1974)
• A.N. Chandorkar, W.S. Khokle and Amarjit Singh, “J-V Characteristics of Tunnelling Schottky Barriers,” International Journal of Electronics, (1974)
• A.N. Chandorkar, W.S. Khokle and Amarjit Singh, “Band Structure effects in Calculations of J-V characteristics of tunnelling Schottky Barriers,” Proc. of Symposium on Solid State Devices, Univ. of Calcutta, Calcutta, (1972)
• A.N. Chandorkar, W.S. Khokle and Amarjit Singh, “Ohmic contacts to GaAs,” Solid State Microwave Devices Symposium, Proc. Of Symposium Univ. of Roorkee, Roorkee, (1971)